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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | a5c4eb3de9deb3a71a6a5230a25ff5962e584980 (patch) | |
| tree | 874b659c6a5eaa1316cde9eb82ec7d08badf638a /src/cpu/simple | |
| parent | e255fa053f8d105de8d188077a318124a3aad9ce (diff) | |
| download | gem5-a5c4eb3de9deb3a71a6a5230a25ff5962e584980.tar.xz | |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/base.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc index 6e8845bf7..b0810517f 100644 --- a/src/cpu/simple/base.cc +++ b/src/cpu/simple/base.cc @@ -435,11 +435,11 @@ BaseSimpleCPU::checkForInterrupts() ThreadContext* tc = thread->getTC(); if (checkInterrupts(tc)) { - Fault interrupt = interrupts->getInterrupt(tc); + Fault interrupt = interrupts[curThread]->getInterrupt(tc); if (interrupt != NoFault) { t_info.fetchOffset = 0; - interrupts->updateIntrInfo(tc); + interrupts[curThread]->updateIntrInfo(tc); interrupt->invoke(tc); thread->decoder.reset(); } |