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authorNilay Vaish <nilay@cs.wisc.edu>2015-07-28 01:58:04 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2015-07-28 01:58:04 -0500
commitaafa5c3f86ea54f5e6e88009be656aeec12eef5f (patch)
treed40f2fd8a807ddc9638f292205754f9ecf19b6ef /src/cpu/simple
parent608641e23c7f2288810c3f23a1a63790b664f2ab (diff)
downloadgem5-aafa5c3f86ea54f5e6e88009be656aeec12eef5f.tar.xz
revert 5af8f40d8f2c
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/base.hh20
1 files changed, 0 insertions, 20 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 27e434132..2f7247010 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -87,7 +87,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
typedef TheISA::CCReg CCReg;
- typedef TheISA::VectorReg VectorReg;
BPredUnit *branchPred;
@@ -240,10 +239,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
Stats::Scalar numCCRegReads;
Stats::Scalar numCCRegWrites;
- //number of vector register file accesses
- Stats::Scalar numVectorRegReads;
- Stats::Scalar numVectorRegWrites;
-
// number of simulated memory references
Stats::Scalar numMemRefs;
Stats::Scalar numLoadInsts;
@@ -330,13 +325,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
return thread->readCCReg(reg_idx);
}
- const VectorReg &readVectorRegOperand(const StaticInst *si, int idx)
- {
- numVectorRegReads++;
- int reg_idx = si->srcRegIdx(idx) - TheISA::Vector_Reg_Base;
- return thread->readVectorReg(reg_idx);
- }
-
void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
{
numIntRegWrites++;
@@ -365,14 +353,6 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
thread->setCCReg(reg_idx, val);
}
- void setVectorRegOperand(const StaticInst *si, int idx,
- const VectorReg &val)
- {
- numVectorRegWrites++;
- int reg_idx = si->destRegIdx(idx) - TheISA::Vector_Reg_Base;
- thread->setVectorReg(reg_idx, val);
- }
-
bool readPredicate() { return thread->readPredicate(); }
void setPredicate(bool val)
{