Merge zizzer.eecs.umich.edu:/bk/newmem/

into  zeep.eecs.umich.edu:/home/gblack/m5/newmemmemops

--HG--
extra : convert_revision : c2f7398a0d14dd11108579bb243ada7420285a22

6 files changed, 6 insertions, 22 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 1e12aadef..72249be41 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -72,15 +72,6 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
 void
 AtomicSimpleCPU::init()
 {
-    //Create Memory Ports (conect them up)
-//    Port *mem_dport = mem->getPort("");
-//    dcachePort.setPeer(mem_dport);
-//    mem_dport->setPeer(&dcachePort);
-
-//    Port *mem_iport = mem->getPort("");
-//    icachePort.setPeer(mem_iport);
-//    mem_iport->setPeer(&icachePort);
-
     BaseCPU::init();
 #if FULL_SYSTEM
     for (int i = 0; i < threadContexts.size(); ++i) {
@@ -508,7 +499,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
     Param<Tick> progress_interval;
-    SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
 
@@ -541,7 +531,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
     INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
 
@@ -579,7 +568,6 @@ CREATE_SIM_OBJECT(AtomicSimpleCPU)
     params->functionTraceStart = function_trace_start;
     params->width = width;
     params->simulate_stalls = simulate_stalls;
-    params->mem = mem;
     params->system = system;
     params->cpu_id = cpu_id;
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 0edca9369..166a18127 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -87,7 +87,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
       public:
 
         CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
-            : Port(_name), cpu(_cpu)
+            : Port(_name, _cpu), cpu(_cpu)
         { }
 
       protected:
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 253d33243..47b3b938f 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -70,13 +70,13 @@ using namespace std;
 using namespace TheISA;
 
 BaseSimpleCPU::BaseSimpleCPU(Params *p)
-    : BaseCPU(p), mem(p->mem), thread(NULL)
+    : BaseCPU(p), thread(NULL)
 {
 #if FULL_SYSTEM
     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
 #else
     thread = new SimpleThread(this, /* thread_num */ 0, p->process,
-            /* asid */ 0, mem);
+            /* asid */ 0);
 #endif // !FULL_SYSTEM
 
     thread->setStatus(ThreadContext::Suspended);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 5c8d569bb..d13be2877 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -79,8 +79,6 @@ class BaseSimpleCPU : public BaseCPU
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
 
-    MemObject *mem;
-
   protected:
     Trace::InstRecord *traceData;
 
@@ -98,7 +96,6 @@ class BaseSimpleCPU : public BaseCPU
   public:
     struct Params : public BaseCPU::Params
     {
-        MemObject *mem;
 #if FULL_SYSTEM
         TheISA::ITB *itb;
         TheISA::DTB *dtb;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 438417882..4d57bf6d5 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -660,7 +660,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     Param<Counter> max_loads_any_thread;
     Param<Counter> max_loads_all_threads;
     Param<Tick> progress_interval;
-    SimObjectParam<MemObject *> mem;
     SimObjectParam<System *> system;
     Param<int> cpu_id;
 
@@ -693,7 +692,6 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
     INIT_PARAM(max_loads_all_threads,
                "terminate when all threads have reached this load count"),
     INIT_PARAM(progress_interval, "Progress interval"),
-    INIT_PARAM(mem, "memory"),
     INIT_PARAM(system, "system object"),
     INIT_PARAM(cpu_id, "processor ID"),
 
@@ -729,7 +727,6 @@ CREATE_SIM_OBJECT(TimingSimpleCPU)
     params->clock = clock;
     params->functionTrace = function_trace;
     params->functionTraceStart = function_trace_start;
-    params->mem = mem;
     params->system = system;
     params->cpu_id = cpu_id;
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 577e13e40..408fa315e 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -79,7 +79,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
       public:
 
         CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
-            : Port(_name), cpu(_cpu), lat(_lat)
+            : Port(_name, _cpu), cpu(_cpu), lat(_lat)
         { }
 
       protected:
@@ -166,6 +166,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
     PacketPtr ifetch_pkt;
     PacketPtr dcache_pkt;
 
+
+
     int cpu_id;
     Tick previousTick;