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authorSteve Reinhardt <stever@eecs.umich.edu>2006-05-22 14:29:33 -0400
committerSteve Reinhardt <stever@eecs.umich.edu>2006-05-22 14:29:33 -0400
commitba2eae5d528487900d1510fc0a160e660f2c394c (patch)
treea2c6dd5948f6ff353763cb3f83ddd734077e646e /src/cpu/simple
parent86777c9db174c74be49667bce3dda99f8ba23696 (diff)
downloadgem5-ba2eae5d528487900d1510fc0a160e660f2c394c.tar.xz
New directory structure:
- simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions. SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure. --HG-- rename : build/SConstruct => SConstruct rename : build/default_options/ALPHA_FS => build_opts/ALPHA_FS rename : build/default_options/ALPHA_FS_TL => build_opts/ALPHA_FS_TL rename : build/default_options/ALPHA_SE => build_opts/ALPHA_SE rename : build/default_options/MIPS_SE => build_opts/MIPS_SE rename : build/default_options/SPARC_SE => build_opts/SPARC_SE rename : Doxyfile => src/Doxyfile rename : SConscript => src/SConscript rename : arch/SConscript => src/arch/SConscript rename : arch/alpha/SConscript => src/arch/alpha/SConscript rename : arch/alpha/aout_machdep.h => src/arch/alpha/aout_machdep.h rename : arch/alpha/arguments.cc => src/arch/alpha/arguments.cc rename : arch/alpha/arguments.hh => src/arch/alpha/arguments.hh rename : arch/alpha/ecoff_machdep.h => src/arch/alpha/ecoff_machdep.h rename : arch/alpha/ev5.cc => src/arch/alpha/ev5.cc rename : arch/alpha/ev5.hh => src/arch/alpha/ev5.hh rename : arch/alpha/faults.cc => src/arch/alpha/faults.cc rename : arch/alpha/faults.hh => src/arch/alpha/faults.hh rename : arch/alpha/freebsd/system.cc => src/arch/alpha/freebsd/system.cc rename : arch/alpha/freebsd/system.hh => src/arch/alpha/freebsd/system.hh rename : arch/alpha/isa/branch.isa => src/arch/alpha/isa/branch.isa rename : arch/alpha/isa/decoder.isa => src/arch/alpha/isa/decoder.isa rename : arch/alpha/isa/fp.isa => src/arch/alpha/isa/fp.isa rename : arch/alpha/isa/int.isa => src/arch/alpha/isa/int.isa rename : arch/alpha/isa/main.isa => src/arch/alpha/isa/main.isa rename : arch/alpha/isa/mem.isa => src/arch/alpha/isa/mem.isa rename : arch/alpha/isa/opcdec.isa => src/arch/alpha/isa/opcdec.isa rename : arch/alpha/isa/pal.isa => src/arch/alpha/isa/pal.isa rename : arch/alpha/isa/unimp.isa => src/arch/alpha/isa/unimp.isa rename : arch/alpha/isa/unknown.isa => src/arch/alpha/isa/unknown.isa rename : arch/alpha/isa/util.isa => src/arch/alpha/isa/util.isa rename : arch/alpha/isa_traits.hh => src/arch/alpha/isa_traits.hh rename : arch/alpha/linux/aligned.hh => src/arch/alpha/linux/aligned.hh rename : arch/alpha/linux/hwrpb.hh => src/arch/alpha/linux/hwrpb.hh rename : arch/alpha/linux/linux.cc => src/arch/alpha/linux/linux.cc rename : arch/alpha/linux/linux.hh => src/arch/alpha/linux/linux.hh rename : arch/alpha/linux/process.cc => src/arch/alpha/linux/process.cc rename : arch/alpha/linux/process.hh => src/arch/alpha/linux/process.hh rename : arch/alpha/linux/system.cc => src/arch/alpha/linux/system.cc rename : arch/alpha/linux/system.hh => src/arch/alpha/linux/system.hh rename : arch/alpha/linux/thread_info.hh => src/arch/alpha/linux/thread_info.hh rename : arch/alpha/linux/threadinfo.hh => src/arch/alpha/linux/threadinfo.hh rename : arch/alpha/osfpal.cc => src/arch/alpha/osfpal.cc rename : arch/alpha/osfpal.hh => src/arch/alpha/osfpal.hh rename : arch/alpha/process.cc => src/arch/alpha/process.cc rename : arch/alpha/process.hh => src/arch/alpha/process.hh rename : arch/alpha/regfile.hh => src/arch/alpha/regfile.hh rename : arch/alpha/stacktrace.cc => src/arch/alpha/stacktrace.cc rename : arch/alpha/stacktrace.hh => src/arch/alpha/stacktrace.hh rename : arch/alpha/system.cc => src/arch/alpha/system.cc rename : arch/alpha/system.hh => src/arch/alpha/system.hh rename : arch/alpha/tlb.cc => src/arch/alpha/tlb.cc rename : arch/alpha/tlb.hh => src/arch/alpha/tlb.hh rename : arch/alpha/tru64/process.cc => src/arch/alpha/tru64/process.cc rename : arch/alpha/tru64/process.hh => src/arch/alpha/tru64/process.hh rename : arch/alpha/tru64/system.cc => src/arch/alpha/tru64/system.cc rename : arch/alpha/tru64/system.hh => src/arch/alpha/tru64/system.hh rename : arch/alpha/tru64/tru64.cc => src/arch/alpha/tru64/tru64.cc rename : arch/alpha/tru64/tru64.hh => src/arch/alpha/tru64/tru64.hh rename : arch/alpha/types.hh => src/arch/alpha/types.hh rename : arch/alpha/utility.hh => src/arch/alpha/utility.hh rename : arch/alpha/vtophys.cc => src/arch/alpha/vtophys.cc rename : arch/alpha/vtophys.hh => src/arch/alpha/vtophys.hh rename : arch/isa_parser.py => src/arch/isa_parser.py rename : arch/isa_specific.hh => src/arch/isa_specific.hh rename : arch/mips/SConscript => src/arch/mips/SConscript rename : arch/mips/faults.cc => src/arch/mips/faults.cc rename : arch/mips/faults.hh => src/arch/mips/faults.hh rename : arch/mips/isa/base.isa => src/arch/mips/isa/base.isa rename : arch/mips/isa/bitfields.isa => src/arch/mips/isa/bitfields.isa rename : arch/mips/isa/decoder.isa => src/arch/mips/isa/decoder.isa rename : arch/mips/isa/formats/basic.isa => src/arch/mips/isa/formats/basic.isa rename : arch/mips/isa/formats/branch.isa => src/arch/mips/isa/formats/branch.isa rename : arch/mips/isa/formats/formats.isa => src/arch/mips/isa/formats/formats.isa rename : arch/mips/isa/formats/fp.isa => src/arch/mips/isa/formats/fp.isa rename : arch/mips/isa/formats/int.isa => src/arch/mips/isa/formats/int.isa rename : arch/mips/isa/formats/mem.isa => src/arch/mips/isa/formats/mem.isa rename : arch/mips/isa/formats/noop.isa => src/arch/mips/isa/formats/noop.isa rename : arch/mips/isa/formats/tlbop.isa => src/arch/mips/isa/formats/tlbop.isa rename : arch/mips/isa/formats/trap.isa => src/arch/mips/isa/formats/trap.isa rename : arch/mips/isa/formats/unimp.isa => src/arch/mips/isa/formats/unimp.isa rename : arch/mips/isa/formats/unknown.isa => src/arch/mips/isa/formats/unknown.isa rename : arch/mips/isa/formats/util.isa => src/arch/mips/isa/formats/util.isa rename : arch/mips/isa/includes.isa => src/arch/mips/isa/includes.isa rename : arch/mips/isa/main.isa => src/arch/mips/isa/main.isa rename : arch/mips/isa/operands.isa => src/arch/mips/isa/operands.isa rename : arch/mips/isa_traits.cc => src/arch/mips/isa_traits.cc rename : arch/mips/isa_traits.hh => src/arch/mips/isa_traits.hh rename : arch/mips/linux/linux.cc => src/arch/mips/linux/linux.cc rename : arch/mips/linux/linux.hh => src/arch/mips/linux/linux.hh rename : arch/mips/linux/process.cc => src/arch/mips/linux/process.cc rename : arch/mips/linux/process.hh => src/arch/mips/linux/process.hh rename : arch/mips/process.cc => src/arch/mips/process.cc rename : arch/mips/process.hh => src/arch/mips/process.hh rename : arch/mips/regfile/float_regfile.hh => src/arch/mips/regfile/float_regfile.hh rename : arch/mips/regfile/int_regfile.hh => src/arch/mips/regfile/int_regfile.hh rename : arch/mips/regfile/misc_regfile.hh => src/arch/mips/regfile/misc_regfile.hh rename : arch/mips/regfile/regfile.hh => src/arch/mips/regfile/regfile.hh rename : arch/mips/stacktrace.hh => src/arch/mips/stacktrace.hh rename : arch/mips/types.hh => src/arch/mips/types.hh rename : arch/mips/utility.hh => src/arch/mips/utility.hh rename : arch/sparc/SConscript => src/arch/sparc/SConscript rename : arch/sparc/faults.cc => src/arch/sparc/faults.cc rename : arch/sparc/faults.hh => src/arch/sparc/faults.hh rename : arch/sparc/isa/base.isa => src/arch/sparc/isa/base.isa rename : arch/sparc/isa/bitfields.isa => src/arch/sparc/isa/bitfields.isa rename : arch/sparc/isa/decoder.isa => src/arch/sparc/isa/decoder.isa rename : arch/sparc/isa/formats.isa => src/arch/sparc/isa/formats.isa rename : arch/sparc/isa/formats/basic.isa => src/arch/sparc/isa/formats/basic.isa rename : arch/sparc/isa/formats/branch.isa => src/arch/sparc/isa/formats/branch.isa rename : arch/sparc/isa/formats/integerop.isa => src/arch/sparc/isa/formats/integerop.isa rename : arch/sparc/isa/formats/mem.isa => src/arch/sparc/isa/formats/mem.isa rename : arch/sparc/isa/formats/nop.isa => src/arch/sparc/isa/formats/nop.isa rename : arch/sparc/isa/formats/priv.isa => src/arch/sparc/isa/formats/priv.isa rename : arch/sparc/isa/formats/trap.isa => src/arch/sparc/isa/formats/trap.isa rename : arch/sparc/isa/formats/unknown.isa => src/arch/sparc/isa/formats/unknown.isa rename : arch/sparc/isa/includes.isa => src/arch/sparc/isa/includes.isa rename : arch/sparc/isa/main.isa => src/arch/sparc/isa/main.isa rename : arch/sparc/isa/operands.isa => src/arch/sparc/isa/operands.isa rename : arch/sparc/isa_traits.hh => src/arch/sparc/isa_traits.hh rename : arch/sparc/linux/linux.cc => src/arch/sparc/linux/linux.cc rename : arch/sparc/linux/linux.hh => src/arch/sparc/linux/linux.hh rename : arch/sparc/linux/process.cc => src/arch/sparc/linux/process.cc rename : arch/sparc/linux/process.hh => src/arch/sparc/linux/process.hh rename : arch/sparc/process.cc => src/arch/sparc/process.cc rename : arch/sparc/process.hh => src/arch/sparc/process.hh rename : arch/sparc/regfile.hh => src/arch/sparc/regfile.hh rename : arch/sparc/solaris/process.cc => src/arch/sparc/solaris/process.cc rename : arch/sparc/solaris/process.hh => src/arch/sparc/solaris/process.hh rename : arch/sparc/solaris/solaris.cc => src/arch/sparc/solaris/solaris.cc rename : arch/sparc/solaris/solaris.hh => src/arch/sparc/solaris/solaris.hh rename : arch/sparc/stacktrace.hh => src/arch/sparc/stacktrace.hh rename : arch/sparc/system.cc => src/arch/sparc/system.cc rename : arch/sparc/system.hh => src/arch/sparc/system.hh rename : arch/sparc/utility.hh => src/arch/sparc/utility.hh rename : base/bitfield.hh => src/base/bitfield.hh rename : base/callback.hh => src/base/callback.hh rename : base/chunk_generator.hh => src/base/chunk_generator.hh rename : base/circlebuf.cc => src/base/circlebuf.cc rename : base/circlebuf.hh => src/base/circlebuf.hh rename : base/compression/lzss_compression.cc => src/base/compression/lzss_compression.cc rename : base/compression/lzss_compression.hh => src/base/compression/lzss_compression.hh rename : base/compression/null_compression.hh => src/base/compression/null_compression.hh rename : base/cprintf.cc => src/base/cprintf.cc rename : base/cprintf.hh => src/base/cprintf.hh rename : base/cprintf_formats.hh => src/base/cprintf_formats.hh rename : base/crc.cc => src/base/crc.cc rename : base/crc.hh => src/base/crc.hh rename : base/date.cc => src/base/date.cc rename : base/dbl_list.hh => src/base/dbl_list.hh rename : base/endian.hh => src/base/endian.hh rename : base/fast_alloc.cc => src/base/fast_alloc.cc rename : base/fast_alloc.hh => src/base/fast_alloc.hh rename : base/fenv.hh => src/base/fenv.hh rename : base/fifo_buffer.cc => src/base/fifo_buffer.cc rename : base/fifo_buffer.hh => src/base/fifo_buffer.hh rename : base/hashmap.hh => src/base/hashmap.hh rename : base/hostinfo.cc => src/base/hostinfo.cc rename : base/hostinfo.hh => src/base/hostinfo.hh rename : base/hybrid_pred.cc => src/base/hybrid_pred.cc rename : base/hybrid_pred.hh => src/base/hybrid_pred.hh rename : base/inet.cc => src/base/inet.cc rename : base/inet.hh => src/base/inet.hh rename : base/inifile.cc => src/base/inifile.cc rename : base/inifile.hh => src/base/inifile.hh rename : base/intmath.cc => src/base/intmath.cc rename : base/intmath.hh => src/base/intmath.hh rename : base/kgdb.h => src/base/kgdb.h rename : base/loader/aout_object.cc => src/base/loader/aout_object.cc rename : base/loader/aout_object.hh => src/base/loader/aout_object.hh rename : base/loader/coff_sym.h => src/base/loader/coff_sym.h rename : base/loader/coff_symconst.h => src/base/loader/coff_symconst.h rename : base/loader/ecoff_object.cc => src/base/loader/ecoff_object.cc rename : base/loader/ecoff_object.hh => src/base/loader/ecoff_object.hh rename : base/loader/elf_object.cc => src/base/loader/elf_object.cc rename : base/loader/elf_object.hh => src/base/loader/elf_object.hh rename : base/loader/exec_aout.h => src/base/loader/exec_aout.h rename : base/loader/exec_ecoff.h => src/base/loader/exec_ecoff.h rename : base/loader/object_file.cc => src/base/loader/object_file.cc rename : base/loader/object_file.hh => src/base/loader/object_file.hh rename : base/loader/symtab.cc => src/base/loader/symtab.cc rename : base/loader/symtab.hh => src/base/loader/symtab.hh rename : base/match.cc => src/base/match.cc rename : base/match.hh => src/base/match.hh rename : base/misc.cc => src/base/misc.cc rename : base/misc.hh => src/base/misc.hh rename : base/mod_num.hh => src/base/mod_num.hh rename : base/mysql.cc => src/base/mysql.cc rename : base/mysql.hh => src/base/mysql.hh rename : base/output.cc => src/base/output.cc rename : base/output.hh => src/base/output.hh rename : base/pollevent.cc => src/base/pollevent.cc rename : base/pollevent.hh => src/base/pollevent.hh rename : base/predictor.hh => src/base/predictor.hh rename : base/random.cc => src/base/random.cc rename : base/random.hh => src/base/random.hh rename : base/range.cc => src/base/range.cc rename : base/range.hh => src/base/range.hh rename : base/refcnt.hh => src/base/refcnt.hh rename : base/remote_gdb.cc => src/base/remote_gdb.cc rename : base/remote_gdb.hh => src/base/remote_gdb.hh rename : base/res_list.hh => src/base/res_list.hh rename : base/sat_counter.cc => src/base/sat_counter.cc rename : base/sat_counter.hh => src/base/sat_counter.hh rename : base/sched_list.hh => src/base/sched_list.hh rename : base/socket.cc => src/base/socket.cc rename : base/socket.hh => src/base/socket.hh rename : base/statistics.cc => src/base/statistics.cc rename : base/statistics.hh => src/base/statistics.hh rename : base/stats/events.cc => src/base/stats/events.cc rename : base/stats/events.hh => src/base/stats/events.hh rename : base/stats/flags.hh => src/base/stats/flags.hh rename : base/stats/mysql.cc => src/base/stats/mysql.cc rename : base/stats/mysql.hh => src/base/stats/mysql.hh rename : base/stats/mysql_run.hh => src/base/stats/mysql_run.hh rename : base/stats/output.hh => src/base/stats/output.hh rename : base/stats/statdb.cc => src/base/stats/statdb.cc rename : base/stats/statdb.hh => src/base/stats/statdb.hh rename : base/stats/text.cc => src/base/stats/text.cc rename : base/stats/text.hh => src/base/stats/text.hh rename : base/stats/types.hh => src/base/stats/types.hh rename : base/stats/visit.cc => src/base/stats/visit.cc rename : base/stats/visit.hh => src/base/stats/visit.hh rename : base/str.cc => src/base/str.cc rename : base/str.hh => src/base/str.hh rename : base/time.cc => src/base/time.cc rename : base/time.hh => src/base/time.hh rename : base/timebuf.hh => src/base/timebuf.hh rename : base/trace.cc => src/base/trace.cc rename : base/trace.hh => src/base/trace.hh rename : base/traceflags.py => src/base/traceflags.py rename : base/userinfo.cc => src/base/userinfo.cc rename : base/userinfo.hh => src/base/userinfo.hh rename : cpu/SConscript => src/cpu/SConscript rename : cpu/base.cc => src/cpu/base.cc rename : cpu/base.hh => src/cpu/base.hh rename : cpu/base_dyn_inst.cc => src/cpu/base_dyn_inst.cc rename : cpu/base_dyn_inst.hh => src/cpu/base_dyn_inst.hh rename : cpu/cpu_exec_context.cc => src/cpu/cpu_exec_context.cc rename : cpu/cpu_exec_context.hh => src/cpu/cpu_exec_context.hh rename : cpu/cpu_models.py => src/cpu/cpu_models.py rename : cpu/exec_context.hh => src/cpu/exec_context.hh rename : cpu/exetrace.cc => src/cpu/exetrace.cc rename : cpu/exetrace.hh => src/cpu/exetrace.hh rename : cpu/inst_seq.hh => src/cpu/inst_seq.hh rename : cpu/intr_control.cc => src/cpu/intr_control.cc rename : cpu/intr_control.hh => src/cpu/intr_control.hh rename : cpu/memtest/memtest.cc => src/cpu/memtest/memtest.cc rename : cpu/memtest/memtest.hh => src/cpu/memtest/memtest.hh rename : cpu/o3/2bit_local_pred.cc => src/cpu/o3/2bit_local_pred.cc rename : cpu/o3/2bit_local_pred.hh => src/cpu/o3/2bit_local_pred.hh rename : cpu/o3/alpha_cpu.cc => src/cpu/o3/alpha_cpu.cc rename : cpu/o3/alpha_cpu.hh => src/cpu/o3/alpha_cpu.hh rename : cpu/o3/alpha_cpu_builder.cc => src/cpu/o3/alpha_cpu_builder.cc rename : cpu/o3/alpha_cpu_impl.hh => src/cpu/o3/alpha_cpu_impl.hh rename : cpu/o3/alpha_dyn_inst.cc => src/cpu/o3/alpha_dyn_inst.cc rename : cpu/o3/alpha_dyn_inst.hh => src/cpu/o3/alpha_dyn_inst.hh rename : cpu/o3/alpha_dyn_inst_impl.hh => src/cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/o3/alpha_impl.hh => src/cpu/o3/alpha_impl.hh rename : cpu/o3/alpha_params.hh => src/cpu/o3/alpha_params.hh rename : cpu/o3/bpred_unit.cc => src/cpu/o3/bpred_unit.cc rename : cpu/o3/bpred_unit.hh => src/cpu/o3/bpred_unit.hh rename : cpu/o3/bpred_unit_impl.hh => src/cpu/o3/bpred_unit_impl.hh rename : cpu/o3/btb.cc => src/cpu/o3/btb.cc rename : cpu/o3/btb.hh => src/cpu/o3/btb.hh rename : cpu/o3/comm.hh => src/cpu/o3/comm.hh rename : cpu/o3/commit.cc => src/cpu/o3/commit.cc rename : cpu/o3/commit.hh => src/cpu/o3/commit.hh rename : cpu/o3/commit_impl.hh => src/cpu/o3/commit_impl.hh rename : cpu/o3/cpu.cc => src/cpu/o3/cpu.cc rename : cpu/o3/cpu.hh => src/cpu/o3/cpu.hh rename : cpu/o3/cpu_policy.hh => src/cpu/o3/cpu_policy.hh rename : cpu/o3/decode.cc => src/cpu/o3/decode.cc rename : cpu/o3/decode.hh => src/cpu/o3/decode.hh rename : cpu/o3/decode_impl.hh => src/cpu/o3/decode_impl.hh rename : cpu/o3/fetch.cc => src/cpu/o3/fetch.cc rename : cpu/o3/fetch.hh => src/cpu/o3/fetch.hh rename : cpu/o3/fetch_impl.hh => src/cpu/o3/fetch_impl.hh rename : cpu/o3/free_list.cc => src/cpu/o3/free_list.cc rename : cpu/o3/free_list.hh => src/cpu/o3/free_list.hh rename : cpu/o3/iew.cc => src/cpu/o3/iew.cc rename : cpu/o3/iew.hh => src/cpu/o3/iew.hh rename : cpu/o3/iew_impl.hh => src/cpu/o3/iew_impl.hh rename : cpu/o3/inst_queue.cc => src/cpu/o3/inst_queue.cc rename : cpu/o3/inst_queue.hh => src/cpu/o3/inst_queue.hh rename : cpu/o3/inst_queue_impl.hh => src/cpu/o3/inst_queue_impl.hh rename : cpu/o3/mem_dep_unit.cc => src/cpu/o3/mem_dep_unit.cc rename : cpu/o3/mem_dep_unit.hh => src/cpu/o3/mem_dep_unit.hh rename : cpu/o3/mem_dep_unit_impl.hh => src/cpu/o3/mem_dep_unit_impl.hh rename : cpu/o3/ras.cc => src/cpu/o3/ras.cc rename : cpu/o3/ras.hh => src/cpu/o3/ras.hh rename : cpu/o3/regfile.hh => src/cpu/o3/regfile.hh rename : cpu/o3/rename.cc => src/cpu/o3/rename.cc rename : cpu/o3/rename.hh => src/cpu/o3/rename.hh rename : cpu/o3/rename_impl.hh => src/cpu/o3/rename_impl.hh rename : cpu/o3/rename_map.cc => src/cpu/o3/rename_map.cc rename : cpu/o3/rename_map.hh => src/cpu/o3/rename_map.hh rename : cpu/o3/rob.cc => src/cpu/o3/rob.cc rename : cpu/o3/rob.hh => src/cpu/o3/rob.hh rename : cpu/o3/rob_impl.hh => src/cpu/o3/rob_impl.hh rename : cpu/o3/sat_counter.cc => src/cpu/o3/sat_counter.cc rename : cpu/o3/sat_counter.hh => src/cpu/o3/sat_counter.hh rename : cpu/o3/store_set.cc => src/cpu/o3/store_set.cc rename : cpu/o3/store_set.hh => src/cpu/o3/store_set.hh rename : cpu/o3/tournament_pred.cc => src/cpu/o3/tournament_pred.cc rename : cpu/o3/tournament_pred.hh => src/cpu/o3/tournament_pred.hh rename : cpu/op_class.cc => src/cpu/op_class.cc rename : cpu/op_class.hh => src/cpu/op_class.hh rename : cpu/ozone/cpu.cc => src/cpu/ozone/cpu.cc rename : cpu/ozone/cpu.hh => src/cpu/ozone/cpu.hh rename : cpu/ozone/cpu_impl.hh => src/cpu/ozone/cpu_impl.hh rename : cpu/ozone/ea_list.cc => src/cpu/ozone/ea_list.cc rename : cpu/ozone/ea_list.hh => src/cpu/ozone/ea_list.hh rename : cpu/pc_event.cc => src/cpu/pc_event.cc rename : cpu/pc_event.hh => src/cpu/pc_event.hh rename : cpu/profile.cc => src/cpu/profile.cc rename : cpu/profile.hh => src/cpu/profile.hh rename : cpu/simple/atomic.cc => src/cpu/simple/atomic.cc rename : cpu/simple/atomic.hh => src/cpu/simple/atomic.hh rename : cpu/simple/base.cc => src/cpu/simple/base.cc rename : cpu/simple/base.hh => src/cpu/simple/base.hh rename : cpu/simple/timing.cc => src/cpu/simple/timing.cc rename : cpu/simple/timing.hh => src/cpu/simple/timing.hh rename : cpu/smt.hh => src/cpu/smt.hh rename : cpu/static_inst.cc => src/cpu/static_inst.cc rename : cpu/static_inst.hh => src/cpu/static_inst.hh rename : cpu/trace/opt_cpu.cc => src/cpu/trace/opt_cpu.cc rename : cpu/trace/opt_cpu.hh => src/cpu/trace/opt_cpu.hh rename : cpu/trace/reader/ibm_reader.cc => src/cpu/trace/reader/ibm_reader.cc rename : cpu/trace/reader/ibm_reader.hh => src/cpu/trace/reader/ibm_reader.hh rename : cpu/trace/reader/itx_reader.cc => src/cpu/trace/reader/itx_reader.cc rename : cpu/trace/reader/itx_reader.hh => src/cpu/trace/reader/itx_reader.hh rename : cpu/trace/reader/m5_reader.cc => src/cpu/trace/reader/m5_reader.cc rename : cpu/trace/reader/m5_reader.hh => src/cpu/trace/reader/m5_reader.hh rename : cpu/trace/reader/mem_trace_reader.cc => src/cpu/trace/reader/mem_trace_reader.cc rename : cpu/trace/reader/mem_trace_reader.hh => src/cpu/trace/reader/mem_trace_reader.hh rename : cpu/trace/trace_cpu.cc => src/cpu/trace/trace_cpu.cc rename : cpu/trace/trace_cpu.hh => src/cpu/trace/trace_cpu.hh rename : dev/alpha_access.h => src/dev/alpha_access.h rename : dev/alpha_console.cc => src/dev/alpha_console.cc rename : dev/alpha_console.hh => src/dev/alpha_console.hh rename : dev/baddev.cc => src/dev/baddev.cc rename : dev/baddev.hh => src/dev/baddev.hh rename : dev/disk_image.cc => src/dev/disk_image.cc rename : dev/disk_image.hh => src/dev/disk_image.hh rename : dev/etherbus.cc => src/dev/etherbus.cc rename : dev/etherbus.hh => src/dev/etherbus.hh rename : dev/etherdump.cc => src/dev/etherdump.cc rename : dev/etherdump.hh => src/dev/etherdump.hh rename : dev/etherint.cc => src/dev/etherint.cc rename : dev/etherint.hh => src/dev/etherint.hh rename : dev/etherlink.cc => src/dev/etherlink.cc rename : dev/etherlink.hh => src/dev/etherlink.hh rename : dev/etherpkt.cc => src/dev/etherpkt.cc rename : dev/etherpkt.hh => src/dev/etherpkt.hh rename : dev/ethertap.cc => src/dev/ethertap.cc rename : dev/ethertap.hh => src/dev/ethertap.hh rename : dev/ide_atareg.h => src/dev/ide_atareg.h rename : dev/ide_ctrl.cc => src/dev/ide_ctrl.cc rename : dev/ide_ctrl.hh => src/dev/ide_ctrl.hh rename : dev/ide_disk.cc => src/dev/ide_disk.cc rename : dev/ide_disk.hh => src/dev/ide_disk.hh rename : dev/ide_wdcreg.h => src/dev/ide_wdcreg.h rename : dev/io_device.cc => src/dev/io_device.cc rename : dev/io_device.hh => src/dev/io_device.hh rename : dev/isa_fake.cc => src/dev/isa_fake.cc rename : dev/isa_fake.hh => src/dev/isa_fake.hh rename : dev/ns_gige.cc => src/dev/ns_gige.cc rename : dev/ns_gige.hh => src/dev/ns_gige.hh rename : dev/ns_gige_reg.h => src/dev/ns_gige_reg.h rename : dev/pciconfigall.cc => src/dev/pciconfigall.cc rename : dev/pciconfigall.hh => src/dev/pciconfigall.hh rename : dev/pcidev.cc => src/dev/pcidev.cc rename : dev/pcidev.hh => src/dev/pcidev.hh rename : dev/pcireg.h => src/dev/pcireg.h rename : dev/pitreg.h => src/dev/pitreg.h rename : dev/pktfifo.cc => src/dev/pktfifo.cc rename : dev/pktfifo.hh => src/dev/pktfifo.hh rename : dev/platform.cc => src/dev/platform.cc rename : dev/platform.hh => src/dev/platform.hh rename : dev/rtcreg.h => src/dev/rtcreg.h rename : dev/simconsole.cc => src/dev/simconsole.cc rename : dev/simconsole.hh => src/dev/simconsole.hh rename : dev/simple_disk.cc => src/dev/simple_disk.cc rename : dev/simple_disk.hh => src/dev/simple_disk.hh rename : dev/sinic.cc => src/dev/sinic.cc rename : dev/sinic.hh => src/dev/sinic.hh rename : dev/sinicreg.hh => src/dev/sinicreg.hh rename : dev/tsunami.cc => src/dev/tsunami.cc rename : dev/tsunami.hh => src/dev/tsunami.hh rename : dev/tsunami_cchip.cc => src/dev/tsunami_cchip.cc rename : dev/tsunami_cchip.hh => src/dev/tsunami_cchip.hh rename : dev/tsunami_io.cc => src/dev/tsunami_io.cc rename : dev/tsunami_io.hh => src/dev/tsunami_io.hh rename : dev/tsunami_pchip.cc => src/dev/tsunami_pchip.cc rename : dev/tsunami_pchip.hh => src/dev/tsunami_pchip.hh rename : dev/tsunamireg.h => src/dev/tsunamireg.h rename : dev/uart.cc => src/dev/uart.cc rename : dev/uart.hh => src/dev/uart.hh rename : dev/uart8250.cc => src/dev/uart8250.cc rename : dev/uart8250.hh => src/dev/uart8250.hh rename : kern/kernel_stats.cc => src/kern/kernel_stats.cc rename : kern/kernel_stats.hh => src/kern/kernel_stats.hh rename : kern/linux/events.cc => src/kern/linux/events.cc rename : kern/linux/events.hh => src/kern/linux/events.hh rename : kern/linux/linux.hh => src/kern/linux/linux.hh rename : kern/linux/linux_syscalls.cc => src/kern/linux/linux_syscalls.cc rename : kern/linux/linux_syscalls.hh => src/kern/linux/linux_syscalls.hh rename : kern/linux/printk.cc => src/kern/linux/printk.cc rename : kern/linux/printk.hh => src/kern/linux/printk.hh rename : kern/linux/sched.hh => src/kern/linux/sched.hh rename : kern/solaris/solaris.hh => src/kern/solaris/solaris.hh rename : kern/system_events.cc => src/kern/system_events.cc rename : kern/system_events.hh => src/kern/system_events.hh rename : kern/tru64/dump_mbuf.cc => src/kern/tru64/dump_mbuf.cc rename : kern/tru64/dump_mbuf.hh => src/kern/tru64/dump_mbuf.hh rename : kern/tru64/mbuf.hh => src/kern/tru64/mbuf.hh rename : kern/tru64/printf.cc => src/kern/tru64/printf.cc rename : kern/tru64/printf.hh => src/kern/tru64/printf.hh rename : kern/tru64/tru64.hh => src/kern/tru64/tru64.hh rename : kern/tru64/tru64_events.cc => src/kern/tru64/tru64_events.cc rename : kern/tru64/tru64_events.hh => src/kern/tru64/tru64_events.hh rename : kern/tru64/tru64_syscalls.cc => src/kern/tru64/tru64_syscalls.cc rename : kern/tru64/tru64_syscalls.hh => src/kern/tru64/tru64_syscalls.hh rename : mem/bridge.cc => src/mem/bridge.cc rename : mem/bridge.hh => src/mem/bridge.hh rename : mem/bus.cc => src/mem/bus.cc rename : mem/bus.hh => src/mem/bus.hh rename : mem/cache/prefetch/tagged_prefetcher_impl.hh => src/mem/cache/prefetch/tagged_prefetcher_impl.hh rename : mem/config/prefetch.hh => src/mem/config/prefetch.hh rename : mem/mem_object.cc => src/mem/mem_object.cc rename : mem/mem_object.hh => src/mem/mem_object.hh rename : mem/packet.cc => src/mem/packet.cc rename : mem/packet.hh => src/mem/packet.hh rename : mem/page_table.cc => src/mem/page_table.cc rename : mem/page_table.hh => src/mem/page_table.hh rename : mem/physical.cc => src/mem/physical.cc rename : mem/physical.hh => src/mem/physical.hh rename : mem/port.cc => src/mem/port.cc rename : mem/port.hh => src/mem/port.hh rename : mem/request.hh => src/mem/request.hh rename : mem/translating_port.cc => src/mem/translating_port.cc rename : mem/translating_port.hh => src/mem/translating_port.hh rename : mem/vport.cc => src/mem/vport.cc rename : mem/vport.hh => src/mem/vport.hh rename : python/SConscript => src/python/SConscript rename : python/m5/__init__.py => src/python/m5/__init__.py rename : python/m5/config.py => src/python/m5/config.py rename : python/m5/convert.py => src/python/m5/convert.py rename : python/m5/multidict.py => src/python/m5/multidict.py rename : python/m5/objects/AlphaConsole.py => src/python/m5/objects/AlphaConsole.py rename : python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaFullCPU.py rename : python/m5/objects/AlphaTLB.py => src/python/m5/objects/AlphaTLB.py rename : python/m5/objects/BadDevice.py => src/python/m5/objects/BadDevice.py rename : python/m5/objects/BaseCPU.py => src/python/m5/objects/BaseCPU.py rename : python/m5/objects/BaseCache.py => src/python/m5/objects/BaseCache.py rename : python/m5/objects/Bridge.py => src/python/m5/objects/Bridge.py rename : python/m5/objects/Bus.py => src/python/m5/objects/Bus.py rename : python/m5/objects/CoherenceProtocol.py => src/python/m5/objects/CoherenceProtocol.py rename : python/m5/objects/Device.py => src/python/m5/objects/Device.py rename : python/m5/objects/DiskImage.py => src/python/m5/objects/DiskImage.py rename : python/m5/objects/Ethernet.py => src/python/m5/objects/Ethernet.py rename : python/m5/objects/Ide.py => src/python/m5/objects/Ide.py rename : python/m5/objects/IntrControl.py => src/python/m5/objects/IntrControl.py rename : python/m5/objects/MemObject.py => src/python/m5/objects/MemObject.py rename : python/m5/objects/MemTest.py => src/python/m5/objects/MemTest.py rename : python/m5/objects/Pci.py => src/python/m5/objects/Pci.py rename : python/m5/objects/PhysicalMemory.py => src/python/m5/objects/PhysicalMemory.py rename : python/m5/objects/Platform.py => src/python/m5/objects/Platform.py rename : python/m5/objects/Process.py => src/python/m5/objects/Process.py rename : python/m5/objects/Repl.py => src/python/m5/objects/Repl.py rename : python/m5/objects/Root.py => src/python/m5/objects/Root.py rename : python/m5/objects/SimConsole.py => src/python/m5/objects/SimConsole.py rename : python/m5/objects/SimpleDisk.py => src/python/m5/objects/SimpleDisk.py rename : python/m5/objects/System.py => src/python/m5/objects/System.py rename : python/m5/objects/Tsunami.py => src/python/m5/objects/Tsunami.py rename : python/m5/objects/Uart.py => src/python/m5/objects/Uart.py rename : python/m5/smartdict.py => src/python/m5/smartdict.py rename : sim/async.hh => src/sim/async.hh rename : sim/builder.cc => src/sim/builder.cc rename : sim/builder.hh => src/sim/builder.hh rename : sim/byteswap.hh => src/sim/byteswap.hh rename : sim/debug.cc => src/sim/debug.cc rename : sim/debug.hh => src/sim/debug.hh rename : sim/eventq.cc => src/sim/eventq.cc rename : sim/eventq.hh => src/sim/eventq.hh rename : sim/faults.cc => src/sim/faults.cc rename : sim/faults.hh => src/sim/faults.hh rename : sim/host.hh => src/sim/host.hh rename : sim/main.cc => src/sim/main.cc rename : sim/param.cc => src/sim/param.cc rename : sim/param.hh => src/sim/param.hh rename : sim/process.cc => src/sim/process.cc rename : sim/process.hh => src/sim/process.hh rename : sim/pseudo_inst.cc => src/sim/pseudo_inst.cc rename : sim/pseudo_inst.hh => src/sim/pseudo_inst.hh rename : sim/root.cc => src/sim/root.cc rename : sim/serialize.cc => src/sim/serialize.cc rename : sim/serialize.hh => src/sim/serialize.hh rename : sim/sim_events.cc => src/sim/sim_events.cc rename : sim/sim_events.hh => src/sim/sim_events.hh rename : sim/sim_exit.hh => src/sim/sim_exit.hh rename : sim/sim_object.cc => src/sim/sim_object.cc rename : sim/sim_object.hh => src/sim/sim_object.hh rename : sim/startup.cc => src/sim/startup.cc rename : sim/startup.hh => src/sim/startup.hh rename : sim/stat_control.cc => src/sim/stat_control.cc rename : sim/stat_control.hh => src/sim/stat_control.hh rename : sim/stats.hh => src/sim/stats.hh rename : sim/syscall_emul.cc => src/sim/syscall_emul.cc rename : sim/syscall_emul.hh => src/sim/syscall_emul.hh rename : sim/system.cc => src/sim/system.cc rename : sim/system.hh => src/sim/system.hh rename : sim/vptr.hh => src/sim/vptr.hh rename : test/Makefile => src/unittest/Makefile rename : test/bitvectest.cc => src/unittest/bitvectest.cc rename : test/circletest.cc => src/unittest/circletest.cc rename : test/cprintftest.cc => src/unittest/cprintftest.cc rename : test/foo.ini => src/unittest/foo.ini rename : test/genini.py => src/unittest/genini.py rename : test/initest.cc => src/unittest/initest.cc rename : test/initest.ini => src/unittest/initest.ini rename : test/lru_test.cc => src/unittest/lru_test.cc rename : test/nmtest.cc => src/unittest/nmtest.cc rename : test/offtest.cc => src/unittest/offtest.cc rename : test/paramtest.cc => src/unittest/paramtest.cc rename : test/rangetest.cc => src/unittest/rangetest.cc rename : test/sized_test.cc => src/unittest/sized_test.cc rename : test/stattest.cc => src/unittest/stattest.cc rename : test/strnumtest.cc => src/unittest/strnumtest.cc rename : test/symtest.cc => src/unittest/symtest.cc rename : test/tokentest.cc => src/unittest/tokentest.cc rename : test/tracetest.cc => src/unittest/tracetest.cc extra : convert_revision : cab6a5271ca1b368193cd948e5d3dcc47ab1bd48
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc560
-rw-r--r--src/cpu/simple/atomic.hh139
-rw-r--r--src/cpu/simple/base.cc478
-rw-r--r--src/cpu/simple/base.hh316
-rw-r--r--src/cpu/simple/timing.cc570
-rw-r--r--src/cpu/simple/timing.hh150
6 files changed, 2213 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
new file mode 100644
index 000000000..e9422b9c0
--- /dev/null
+++ b/src/cpu/simple/atomic.cc
@@ -0,0 +1,560 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/utility.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/simple/atomic.hh"
+#include "mem/packet_impl.hh"
+#include "sim/builder.hh"
+
+using namespace std;
+using namespace TheISA;
+
+AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
+ : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
+{
+}
+
+
+void
+AtomicSimpleCPU::TickEvent::process()
+{
+ cpu->tick();
+}
+
+const char *
+AtomicSimpleCPU::TickEvent::description()
+{
+ return "AtomicSimpleCPU tick event";
+}
+
+
+void
+AtomicSimpleCPU::init()
+{
+ //Create Memory Ports (conect them up)
+ Port *mem_dport = mem->getPort("");
+ dcachePort.setPeer(mem_dport);
+ mem_dport->setPeer(&dcachePort);
+
+ Port *mem_iport = mem->getPort("");
+ icachePort.setPeer(mem_iport);
+ mem_iport->setPeer(&icachePort);
+
+ BaseCPU::init();
+#if FULL_SYSTEM
+ for (int i = 0; i < execContexts.size(); ++i) {
+ ExecContext *xc = execContexts[i];
+
+ // initialize CPU, including PC
+ TheISA::initCPU(xc, xc->readCpuId());
+ }
+#endif
+}
+
+bool
+AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
+{
+ panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
+ return true;
+}
+
+Tick
+AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+{
+ panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
+ return curTick;
+}
+
+void
+AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+{
+ panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
+}
+
+void
+AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
+{
+ if (status == RangeChange)
+ return;
+
+ panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
+}
+
+Packet *
+AtomicSimpleCPU::CpuPort::recvRetry()
+{
+ panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
+ return NULL;
+}
+
+
+AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
+ : BaseSimpleCPU(p), tickEvent(this),
+ width(p->width), simulate_stalls(p->simulate_stalls),
+ icachePort(this), dcachePort(this)
+{
+ _status = Idle;
+
+ ifetch_req = new Request(true);
+ ifetch_req->setAsid(0);
+ // @todo fix me and get the real cpu iD!!!
+ ifetch_req->setCpuNum(0);
+ ifetch_req->setSize(sizeof(MachInst));
+ ifetch_pkt = new Packet;
+ ifetch_pkt->cmd = Read;
+ ifetch_pkt->dataStatic(&inst);
+ ifetch_pkt->req = ifetch_req;
+ ifetch_pkt->size = sizeof(MachInst);
+ ifetch_pkt->dest = Packet::Broadcast;
+
+ data_read_req = new Request(true);
+ // @todo fix me and get the real cpu iD!!!
+ data_read_req->setCpuNum(0);
+ data_read_req->setAsid(0);
+ data_read_pkt = new Packet;
+ data_read_pkt->cmd = Read;
+ data_read_pkt->dataStatic(&dataReg);
+ data_read_pkt->req = data_read_req;
+ data_read_pkt->dest = Packet::Broadcast;
+
+ data_write_req = new Request(true);
+ // @todo fix me and get the real cpu iD!!!
+ data_write_req->setCpuNum(0);
+ data_write_req->setAsid(0);
+ data_write_pkt = new Packet;
+ data_write_pkt->cmd = Write;
+ data_write_pkt->req = data_write_req;
+ data_write_pkt->dest = Packet::Broadcast;
+}
+
+
+AtomicSimpleCPU::~AtomicSimpleCPU()
+{
+}
+
+void
+AtomicSimpleCPU::serialize(ostream &os)
+{
+ BaseSimpleCPU::serialize(os);
+ SERIALIZE_ENUM(_status);
+ nameOut(os, csprintf("%s.tickEvent", name()));
+ tickEvent.serialize(os);
+}
+
+void
+AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
+{
+ BaseSimpleCPU::unserialize(cp, section);
+ UNSERIALIZE_ENUM(_status);
+ tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
+}
+
+void
+AtomicSimpleCPU::switchOut(Sampler *s)
+{
+ sampler = s;
+ if (status() == Running) {
+ _status = SwitchedOut;
+
+ tickEvent.squash();
+ }
+ sampler->signalSwitched();
+}
+
+
+void
+AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
+{
+ BaseCPU::takeOverFrom(oldCPU);
+
+ assert(!tickEvent.scheduled());
+
+ // if any of this CPU's ExecContexts are active, mark the CPU as
+ // running and schedule its tick event.
+ for (int i = 0; i < execContexts.size(); ++i) {
+ ExecContext *xc = execContexts[i];
+ if (xc->status() == ExecContext::Active && _status != Running) {
+ _status = Running;
+ tickEvent.schedule(curTick);
+ break;
+ }
+ }
+}
+
+
+void
+AtomicSimpleCPU::activateContext(int thread_num, int delay)
+{
+ assert(thread_num == 0);
+ assert(cpuXC);
+
+ assert(_status == Idle);
+ assert(!tickEvent.scheduled());
+
+ notIdleFraction++;
+ tickEvent.schedule(curTick + cycles(delay));
+ _status = Running;
+}
+
+
+void
+AtomicSimpleCPU::suspendContext(int thread_num)
+{
+ assert(thread_num == 0);
+ assert(cpuXC);
+
+ assert(_status == Running);
+
+ // tick event may not be scheduled if this gets called from inside
+ // an instruction's execution, e.g. "quiesce"
+ if (tickEvent.scheduled())
+ tickEvent.deschedule();
+
+ notIdleFraction--;
+ _status = Idle;
+}
+
+
+template <class T>
+Fault
+AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
+{
+ data_read_req->setVaddr(addr);
+ data_read_req->setSize(sizeof(T));
+ data_read_req->setFlags(flags);
+ data_read_req->setTime(curTick);
+
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
+ // translate to physical address
+ Fault fault = cpuXC->translateDataReadReq(data_read_req);
+
+ // Now do the access.
+ if (fault == NoFault) {
+ data_read_pkt->reset();
+ data_read_pkt->addr = data_read_req->getPaddr();
+ data_read_pkt->size = sizeof(T);
+
+ dcache_complete = dcachePort.sendAtomic(data_read_pkt);
+ dcache_access = true;
+
+ assert(data_read_pkt->result == Success);
+ data = data_read_pkt->get<T>();
+
+ }
+
+ // This will need a new way to tell if it has a dcache attached.
+ if (data_read_req->getFlags() & UNCACHEABLE)
+ recordEvent("Uncached Read");
+
+ return fault;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
+
+template
+Fault
+AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
+
+template
+Fault
+AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
+
+template
+Fault
+AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
+{
+ return read(addr, *(uint64_t*)&data, flags);
+}
+
+template<>
+Fault
+AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
+{
+ return read(addr, *(uint32_t*)&data, flags);
+}
+
+
+template<>
+Fault
+AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
+{
+ return read(addr, (uint32_t&)data, flags);
+}
+
+
+template <class T>
+Fault
+AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+{
+ data_write_req->setVaddr(addr);
+ data_write_req->setTime(curTick);
+ data_write_req->setSize(sizeof(T));
+ data_write_req->setFlags(flags);
+
+ if (traceData) {
+ traceData->setAddr(addr);
+ }
+
+ // translate to physical address
+ Fault fault = cpuXC->translateDataWriteReq(data_write_req);
+
+ // Now do the access.
+ if (fault == NoFault) {
+ data_write_pkt->reset();
+ data = htog(data);
+ data_write_pkt->dataStatic(&data);
+ data_write_pkt->addr = data_write_req->getPaddr();
+ data_write_pkt->size = sizeof(T);
+
+ dcache_complete = dcachePort.sendAtomic(data_write_pkt);
+ dcache_access = true;
+
+ assert(data_write_pkt->result == Success);
+
+ if (res && data_write_req->getFlags() & LOCKED) {
+ *res = data_write_req->getScResult();
+ }
+ }
+
+ // This will need a new way to tell if it's hooked up to a cache or not.
+ if (data_write_req->getFlags() & UNCACHEABLE)
+ recordEvent("Uncached Write");
+
+ // If the write needs to have a fault on the access, consider calling
+ // changeStatus() and changing it to "bad addr write" or something.
+ return fault;
+}
+
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+template
+Fault
+AtomicSimpleCPU::write(uint64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(uint32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(uint16_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+AtomicSimpleCPU::write(uint8_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write(*(uint64_t*)&data, addr, flags, res);
+}
+
+template<>
+Fault
+AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write(*(uint32_t*)&data, addr, flags, res);
+}
+
+
+template<>
+Fault
+AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write((uint32_t)data, addr, flags, res);
+}
+
+
+void
+AtomicSimpleCPU::tick()
+{
+ Tick latency = cycles(1); // instruction takes one cycle by default
+
+ for (int i = 0; i < width; ++i) {
+ numCycles++;
+
+ checkForInterrupts();
+
+ ifetch_req->resetMin();
+ ifetch_pkt->reset();
+ Fault fault = setupFetchPacket(ifetch_pkt);
+
+ if (fault == NoFault) {
+ Tick icache_complete = icachePort.sendAtomic(ifetch_pkt);
+ // ifetch_req is initialized to read the instruction directly
+ // into the CPU object's inst field.
+
+ dcache_access = false; // assume no dcache access
+ preExecute();
+ fault = curStaticInst->execute(this, traceData);
+ postExecute();
+
+ if (traceData) {
+ traceData->finalize();
+ }
+
+ if (simulate_stalls) {
+ // This calculation assumes that the icache and dcache
+ // access latencies are always a multiple of the CPU's
+ // cycle time. If not, the next tick event may get
+ // scheduled at a non-integer multiple of the CPU
+ // cycle time.
+ Tick icache_stall = icache_complete - curTick - cycles(1);
+ Tick dcache_stall =
+ dcache_access ? dcache_complete - curTick - cycles(1) : 0;
+ latency += icache_stall + dcache_stall;
+ }
+
+ }
+
+ advancePC(fault);
+ }
+
+ if (_status != Idle)
+ tickEvent.schedule(curTick + latency);
+}
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// AtomicSimpleCPU Simulation Object
+//
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
+
+ Param<Counter> max_insts_any_thread;
+ Param<Counter> max_insts_all_threads;
+ Param<Counter> max_loads_any_thread;
+ Param<Counter> max_loads_all_threads;
+ SimObjectParam<MemObject *> mem;
+
+#if FULL_SYSTEM
+ SimObjectParam<AlphaITB *> itb;
+ SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<System *> system;
+ Param<int> cpu_id;
+ Param<Tick> profile;
+#else
+ SimObjectParam<Process *> workload;
+#endif // FULL_SYSTEM
+
+ Param<int> clock;
+
+ Param<bool> defer_registration;
+ Param<int> width;
+ Param<bool> function_trace;
+ Param<Tick> function_trace_start;
+ Param<bool> simulate_stalls;
+
+END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
+
+ INIT_PARAM(max_insts_any_thread,
+ "terminate when any thread reaches this inst count"),
+ INIT_PARAM(max_insts_all_threads,
+ "terminate when all threads have reached this inst count"),
+ INIT_PARAM(max_loads_any_thread,
+ "terminate when any thread reaches this load count"),
+ INIT_PARAM(max_loads_all_threads,
+ "terminate when all threads have reached this load count"),
+ INIT_PARAM(mem, "memory"),
+
+#if FULL_SYSTEM
+ INIT_PARAM(itb, "Instruction TLB"),
+ INIT_PARAM(dtb, "Data TLB"),
+ INIT_PARAM(system, "system object"),
+ INIT_PARAM(cpu_id, "processor ID"),
+ INIT_PARAM(profile, ""),
+#else
+ INIT_PARAM(workload, "processes to run"),
+#endif // FULL_SYSTEM
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+ INIT_PARAM(width, "cpu width"),
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace"),
+ INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
+
+END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
+
+
+CREATE_SIM_OBJECT(AtomicSimpleCPU)
+{
+ AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
+ params->name = getInstanceName();
+ params->numberOfThreads = 1;
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
+ params->deferRegistration = defer_registration;
+ params->clock = clock;
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+ params->width = width;
+ params->simulate_stalls = simulate_stalls;
+ params->mem = mem;
+
+#if FULL_SYSTEM
+ params->itb = itb;
+ params->dtb = dtb;
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->profile = profile;
+#else
+ params->process = workload;
+#endif
+
+ AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
+
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
new file mode 100644
index 000000000..d0ba085f0
--- /dev/null
+++ b/src/cpu/simple/atomic.hh
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_SIMPLE_ATOMIC_HH__
+#define __CPU_SIMPLE_ATOMIC_HH__
+
+#include "cpu/simple/base.hh"
+
+class AtomicSimpleCPU : public BaseSimpleCPU
+{
+ public:
+
+ struct Params : public BaseSimpleCPU::Params {
+ int width;
+ bool simulate_stalls;
+ };
+
+ AtomicSimpleCPU(Params *params);
+ virtual ~AtomicSimpleCPU();
+
+ virtual void init();
+
+ public:
+ //
+ enum Status {
+ Running,
+ Idle,
+ SwitchedOut
+ };
+
+ protected:
+ Status _status;
+
+ Status status() const { return _status; }
+
+ private:
+
+ struct TickEvent : public Event
+ {
+ AtomicSimpleCPU *cpu;
+
+ TickEvent(AtomicSimpleCPU *c);
+ void process();
+ const char *description();
+ };
+
+ TickEvent tickEvent;
+
+ const int width;
+ const bool simulate_stalls;
+
+ // main simulation loop (one cycle)
+ void tick();
+
+ class CpuPort : public Port
+ {
+
+ AtomicSimpleCPU *cpu;
+
+ public:
+
+ CpuPort(AtomicSimpleCPU *_cpu)
+ : cpu(_cpu)
+ { }
+
+ protected:
+
+ virtual bool recvTiming(Packet *pkt);
+
+ virtual Tick recvAtomic(Packet *pkt);
+
+ virtual void recvFunctional(Packet *pkt);
+
+ virtual void recvStatusChange(Status status);
+
+ virtual Packet *recvRetry();
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
+ { resp.clear(); snoop.clear(); }
+ };
+
+ CpuPort icachePort;
+ CpuPort dcachePort;
+
+ Request *ifetch_req;
+ Packet *ifetch_pkt;
+ Request *data_read_req;
+ Packet *data_read_pkt;
+ Request *data_write_req;
+ Packet *data_write_pkt;
+
+ bool dcache_access;
+ Tick dcache_complete;
+
+ public:
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+ void switchOut(Sampler *s);
+ void takeOverFrom(BaseCPU *oldCPU);
+
+ virtual void activateContext(int thread_num, int delay);
+ virtual void suspendContext(int thread_num);
+
+ template <class T>
+ Fault read(Addr addr, T &data, unsigned flags);
+
+ template <class T>
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+};
+
+#endif // __CPU_SIMPLE_ATOMIC_HH__
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
new file mode 100644
index 000000000..30c002ed5
--- /dev/null
+++ b/src/cpu/simple/base.cc
@@ -0,0 +1,478 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/utility.hh"
+#include "base/cprintf.hh"
+#include "base/inifile.hh"
+#include "base/loader/symtab.hh"
+#include "base/misc.hh"
+#include "base/pollevent.hh"
+#include "base/range.hh"
+#include "base/stats/events.hh"
+#include "base/trace.hh"
+#include "cpu/base.hh"
+#include "cpu/cpu_exec_context.hh"
+#include "cpu/exec_context.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/profile.hh"
+#include "cpu/sampler/sampler.hh"
+#include "cpu/simple/base.hh"
+#include "cpu/smt.hh"
+#include "cpu/static_inst.hh"
+#include "kern/kernel_stats.hh"
+#include "mem/packet_impl.hh"
+#include "sim/byteswap.hh"
+#include "sim/builder.hh"
+#include "sim/debug.hh"
+#include "sim/host.hh"
+#include "sim/sim_events.hh"
+#include "sim/sim_object.hh"
+#include "sim/stats.hh"
+
+#if FULL_SYSTEM
+#include "base/remote_gdb.hh"
+#include "sim/system.hh"
+#include "arch/tlb.hh"
+#include "arch/stacktrace.hh"
+#include "arch/vtophys.hh"
+#else // !FULL_SYSTEM
+#include "mem/mem_object.hh"
+#endif // FULL_SYSTEM
+
+using namespace std;
+using namespace TheISA;
+
+BaseSimpleCPU::BaseSimpleCPU(Params *p)
+ : BaseCPU(p), mem(p->mem), cpuXC(NULL)
+{
+#if FULL_SYSTEM
+ cpuXC = new CPUExecContext(this, 0, p->system, p->itb, p->dtb);
+#else
+ cpuXC = new CPUExecContext(this, /* thread_num */ 0, p->process,
+ /* asid */ 0, mem);
+#endif // !FULL_SYSTEM
+
+ xcProxy = cpuXC->getProxy();
+
+ numInst = 0;
+ startNumInst = 0;
+ numLoad = 0;
+ startNumLoad = 0;
+ lastIcacheStall = 0;
+ lastDcacheStall = 0;
+
+ execContexts.push_back(xcProxy);
+}
+
+BaseSimpleCPU::~BaseSimpleCPU()
+{
+}
+
+void
+BaseSimpleCPU::deallocateContext(int thread_num)
+{
+ // for now, these are equivalent
+ suspendContext(thread_num);
+}
+
+
+void
+BaseSimpleCPU::haltContext(int thread_num)
+{
+ // for now, these are equivalent
+ suspendContext(thread_num);
+}
+
+
+void
+BaseSimpleCPU::regStats()
+{
+ using namespace Stats;
+
+ BaseCPU::regStats();
+
+ numInsts
+ .name(name() + ".num_insts")
+ .desc("Number of instructions executed")
+ ;
+
+ numMemRefs
+ .name(name() + ".num_refs")
+ .desc("Number of memory references")
+ ;
+
+ notIdleFraction
+ .name(name() + ".not_idle_fraction")
+ .desc("Percentage of non-idle cycles")
+ ;
+
+ idleFraction
+ .name(name() + ".idle_fraction")
+ .desc("Percentage of idle cycles")
+ ;
+
+ icacheStallCycles
+ .name(name() + ".icache_stall_cycles")
+ .desc("ICache total stall cycles")
+ .prereq(icacheStallCycles)
+ ;
+
+ dcacheStallCycles
+ .name(name() + ".dcache_stall_cycles")
+ .desc("DCache total stall cycles")
+ .prereq(dcacheStallCycles)
+ ;
+
+ icacheRetryCycles
+ .name(name() + ".icache_retry_cycles")
+ .desc("ICache total retry cycles")
+ .prereq(icacheRetryCycles)
+ ;
+
+ dcacheRetryCycles
+ .name(name() + ".dcache_retry_cycles")
+ .desc("DCache total retry cycles")
+ .prereq(dcacheRetryCycles)
+ ;
+
+ idleFraction = constant(1.0) - notIdleFraction;
+}
+
+void
+BaseSimpleCPU::resetStats()
+{
+ startNumInst = numInst;
+ // notIdleFraction = (_status != Idle);
+}
+
+void
+BaseSimpleCPU::serialize(ostream &os)
+{
+ BaseCPU::serialize(os);
+ SERIALIZE_SCALAR(inst);
+ nameOut(os, csprintf("%s.xc", name()));
+ cpuXC->serialize(os);
+}
+
+void
+BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
+{
+ BaseCPU::unserialize(cp, section);
+ UNSERIALIZE_SCALAR(inst);
+ cpuXC->unserialize(cp, csprintf("%s.xc", section));
+}
+
+void
+change_thread_state(int thread_number, int activate, int priority)
+{
+}
+
+Fault
+BaseSimpleCPU::copySrcTranslate(Addr src)
+{
+#if 0
+ static bool no_warn = true;
+ int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ // Only support block sizes of 64 atm.
+ assert(blk_size == 64);
+ int offset = src & (blk_size - 1);
+
+ // Make sure block doesn't span page
+ if (no_warn &&
+ (src & PageMask) != ((src + blk_size) & PageMask) &&
+ (src >> 40) != 0xfffffc) {
+ warn("Copied block source spans pages %x.", src);
+ no_warn = false;
+ }
+
+ memReq->reset(src & ~(blk_size - 1), blk_size);
+
+ // translate to physical address
+ Fault fault = cpuXC->translateDataReadReq(req);
+
+ if (fault == NoFault) {
+ cpuXC->copySrcAddr = src;
+ cpuXC->copySrcPhysAddr = memReq->paddr + offset;
+ } else {
+ assert(!fault->isAlignmentFault());
+
+ cpuXC->copySrcAddr = 0;
+ cpuXC->copySrcPhysAddr = 0;
+ }
+ return fault;
+#else
+ return NoFault;
+#endif
+}
+
+Fault
+BaseSimpleCPU::copy(Addr dest)
+{
+#if 0
+ static bool no_warn = true;
+ int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
+ // Only support block sizes of 64 atm.
+ assert(blk_size == 64);
+ uint8_t data[blk_size];
+ //assert(cpuXC->copySrcAddr);
+ int offset = dest & (blk_size - 1);
+
+ // Make sure block doesn't span page
+ if (no_warn &&
+ (dest & PageMask) != ((dest + blk_size) & PageMask) &&
+ (dest >> 40) != 0xfffffc) {
+ no_warn = false;
+ warn("Copied block destination spans pages %x. ", dest);
+ }
+
+ memReq->reset(dest & ~(blk_size -1), blk_size);
+ // translate to physical address
+ Fault fault = cpuXC->translateDataWriteReq(req);
+
+ if (fault == NoFault) {
+ Addr dest_addr = memReq->paddr + offset;
+ // Need to read straight from memory since we have more than 8 bytes.
+ memReq->paddr = cpuXC->copySrcPhysAddr;
+ cpuXC->mem->read(memReq, data);
+ memReq->paddr = dest_addr;
+ cpuXC->mem->write(memReq, data);
+ if (dcacheInterface) {
+ memReq->cmd = Copy;
+ memReq->completionEvent = NULL;
+ memReq->paddr = cpuXC->copySrcPhysAddr;
+ memReq->dest = dest_addr;
+ memReq->size = 64;
+ memReq->time = curTick;
+ memReq->flags &= ~INST_READ;
+ dcacheInterface->access(memReq);
+ }
+ }
+ else
+ assert(!fault->isAlignmentFault());
+
+ return fault;
+#else
+ panic("copy not implemented");
+ return NoFault;
+#endif
+}
+
+#if FULL_SYSTEM
+Addr
+BaseSimpleCPU::dbg_vtophys(Addr addr)
+{
+ return vtophys(xcProxy, addr);
+}
+#endif // FULL_SYSTEM
+
+#if FULL_SYSTEM
+void
+BaseSimpleCPU::post_interrupt(int int_num, int index)
+{
+ BaseCPU::post_interrupt(int_num, index);
+
+ if (cpuXC->status() == ExecContext::Suspended) {
+ DPRINTF(IPI,"Suspended Processor awoke\n");
+ cpuXC->activate();
+ }
+}
+#endif // FULL_SYSTEM
+
+void
+BaseSimpleCPU::checkForInterrupts()
+{
+#if FULL_SYSTEM
+ if (checkInterrupts && check_interrupts() && !cpuXC->inPalMode()) {
+ int ipl = 0;
+ int summary = 0;
+ checkInterrupts = false;
+
+ if (cpuXC->readMiscReg(IPR_SIRR)) {
+ for (int i = INTLEVEL_SOFTWARE_MIN;
+ i < INTLEVEL_SOFTWARE_MAX; i++) {
+ if (cpuXC->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
+ // See table 4-19 of 21164 hardware reference
+ ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
+ summary |= (ULL(1) << i);
+ }
+ }
+ }
+
+ uint64_t interrupts = cpuXC->cpu->intr_status();
+ for (int i = INTLEVEL_EXTERNAL_MIN;
+ i < INTLEVEL_EXTERNAL_MAX; i++) {
+ if (interrupts & (ULL(1) << i)) {
+ // See table 4-19 of 21164 hardware reference
+ ipl = i;
+ summary |= (ULL(1) << i);
+ }
+ }
+
+ if (cpuXC->readMiscReg(IPR_ASTRR))
+ panic("asynchronous traps not implemented\n");
+
+ if (ipl && ipl > cpuXC->readMiscReg(IPR_IPLR)) {
+ cpuXC->setMiscReg(IPR_ISR, summary);
+ cpuXC->setMiscReg(IPR_INTID, ipl);
+
+ Fault(new InterruptFault)->invoke(xcProxy);
+
+ DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
+ cpuXC->readMiscReg(IPR_IPLR), ipl, summary);
+ }
+ }
+#endif
+}
+
+
+Fault
+BaseSimpleCPU::setupFetchPacket(Packet *ifetch_pkt)
+{
+ // Try to fetch an instruction
+
+ // set up memory request for instruction fetch
+
+ DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC->readPC(),
+ cpuXC->readNextPC(),cpuXC->readNextNPC());
+
+ Request *ifetch_req = ifetch_pkt->req;
+ ifetch_req->setVaddr(cpuXC->readPC() & ~3);
+ ifetch_req->setTime(curTick);
+#if FULL_SYSTEM
+ ifetch_req->setFlags((cpuXC->readPC() & 1) ? PHYSICAL : 0);
+#else
+ ifetch_req->setFlags(0);
+#endif
+
+ Fault fault = cpuXC->translateInstReq(ifetch_req);
+
+ if (fault == NoFault) {
+ ifetch_pkt->addr = ifetch_req->getPaddr();
+ }
+
+ return fault;
+}
+
+
+void
+BaseSimpleCPU::preExecute()
+{
+ // maintain $r0 semantics
+ cpuXC->setIntReg(ZeroReg, 0);
+#if THE_ISA == ALPHA_ISA
+ cpuXC->setFloatReg(ZeroReg, 0.0);
+#endif // ALPHA_ISA
+
+ // keep an instruction count
+ numInst++;
+ numInsts++;
+
+ cpuXC->func_exe_inst++;
+
+ // check for instruction-count-based events
+ comInstEventQueue[0]->serviceEvents(numInst);
+
+ // decode the instruction
+ inst = gtoh(inst);
+ curStaticInst = StaticInst::decode(makeExtMI(inst, cpuXC->readPC()));
+
+ traceData = Trace::getInstRecord(curTick, xcProxy, this, curStaticInst,
+ cpuXC->readPC());
+
+ DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
+ curStaticInst->getName(), curStaticInst->getOpcode(),
+ curStaticInst->machInst);
+
+#if FULL_SYSTEM
+ cpuXC->setInst(inst);
+#endif // FULL_SYSTEM
+}
+
+void
+BaseSimpleCPU::postExecute()
+{
+#if FULL_SYSTEM
+ if (system->kernelBinning->fnbin) {
+ assert(kernelStats);
+ system->kernelBinning->execute(xcProxy, inst);
+ }
+
+ if (cpuXC->profile) {
+ bool usermode =
+ (cpuXC->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
+ cpuXC->profilePC = usermode ? 1 : cpuXC->readPC();
+ ProfileNode *node = cpuXC->profile->consume(xcProxy, inst);
+ if (node)
+ cpuXC->profileNode = node;
+ }
+#endif
+
+ if (curStaticInst->isMemRef()) {
+ numMemRefs++;
+ }
+
+ if (curStaticInst->isLoad()) {
+ ++numLoad;
+ comLoadEventQueue[0]->serviceEvents(numLoad);
+ }
+
+ traceFunctions(cpuXC->readPC());
+}
+
+
+void
+BaseSimpleCPU::advancePC(Fault fault)
+{
+ if (fault != NoFault) {
+#if FULL_SYSTEM
+ fault->invoke(xcProxy);
+#else // !FULL_SYSTEM
+ fatal("fault (%s) detected @ PC %08p", fault->name(), cpuXC->readPC());
+#endif // FULL_SYSTEM
+ }
+ else {
+ // go to the next instruction
+ cpuXC->setPC(cpuXC->readNextPC());
+#if THE_ISA == ALPHA_ISA
+ cpuXC->setNextPC(cpuXC->readNextPC() + sizeof(MachInst));
+#else
+ cpuXC->setNextPC(cpuXC->readNextNPC());
+ cpuXC->setNextNPC(cpuXC->readNextNPC() + sizeof(MachInst));
+#endif
+
+ }
+
+#if FULL_SYSTEM
+ Addr oldpc;
+ do {
+ oldpc = cpuXC->readPC();
+ system->pcEventQueue.service(xcProxy);
+ } while (oldpc != cpuXC->readPC());
+#endif
+}
+
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
new file mode 100644
index 000000000..4c0e6f3c7
--- /dev/null
+++ b/src/cpu/simple/base.hh
@@ -0,0 +1,316 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_SIMPLE_BASE_HH__
+#define __CPU_SIMPLE_BASE_HH__
+
+#include "base/statistics.hh"
+#include "config/full_system.hh"
+#include "cpu/base.hh"
+#include "cpu/cpu_exec_context.hh"
+#include "cpu/pc_event.hh"
+#include "cpu/sampler/sampler.hh"
+#include "cpu/static_inst.hh"
+#include "mem/packet.hh"
+#include "mem/port.hh"
+#include "mem/request.hh"
+#include "sim/eventq.hh"
+
+// forward declarations
+#if FULL_SYSTEM
+class Processor;
+class AlphaITB;
+class AlphaDTB;
+class MemObject;
+
+class RemoteGDB;
+class GDBListener;
+
+#else
+
+class Process;
+
+#endif // FULL_SYSTEM
+
+class ExecContext;
+class Checkpoint;
+
+namespace Trace {
+ class InstRecord;
+}
+
+
+class BaseSimpleCPU : public BaseCPU
+{
+ protected:
+ typedef TheISA::MachInst MachInst;
+ typedef TheISA::MiscReg MiscReg;
+ typedef TheISA::FloatReg FloatReg;
+ typedef TheISA::FloatRegBits FloatRegBits;
+
+ MemObject *mem;
+
+ protected:
+ Trace::InstRecord *traceData;
+
+ public:
+ void post_interrupt(int int_num, int index);
+
+ void zero_fill_64(Addr addr) {
+ static int warned = 0;
+ if (!warned) {
+ warn ("WH64 is not implemented");
+ warned = 1;
+ }
+ };
+
+ public:
+ struct Params : public BaseCPU::Params
+ {
+ MemObject *mem;
+#if FULL_SYSTEM
+ AlphaITB *itb;
+ AlphaDTB *dtb;
+#else
+ Process *process;
+#endif
+ };
+ BaseSimpleCPU(Params *params);
+ virtual ~BaseSimpleCPU();
+
+ public:
+ // execution context
+ CPUExecContext *cpuXC;
+
+ ExecContext *xcProxy;
+
+#if FULL_SYSTEM
+ Addr dbg_vtophys(Addr addr);
+
+ bool interval_stats;
+#endif
+
+ // current instruction
+ MachInst inst;
+
+ // Static data storage
+ TheISA::IntReg dataReg;
+
+ // Pointer to the sampler that is telling us to switchover.
+ // Used to signal the completion of the pipe drain and schedule
+ // the next switchover
+ Sampler *sampler;
+
+ StaticInstPtr curStaticInst;
+
+ void checkForInterrupts();
+ Fault setupFetchPacket(Packet *ifetch_pkt);
+ void preExecute();
+ void postExecute();
+ void advancePC(Fault fault);
+
+ virtual void deallocateContext(int thread_num);
+ virtual void haltContext(int thread_num);
+
+ // statistics
+ virtual void regStats();
+ virtual void resetStats();
+
+ // number of simulated instructions
+ Counter numInst;
+ Counter startNumInst;
+ Stats::Scalar<> numInsts;
+
+ virtual Counter totalInstructions() const
+ {
+ return numInst - startNumInst;
+ }
+
+ // number of simulated memory references
+ Stats::Scalar<> numMemRefs;
+
+ // number of simulated loads
+ Counter numLoad;
+ Counter startNumLoad;
+
+ // number of idle cycles
+ Stats::Average<> notIdleFraction;
+ Stats::Formula idleFraction;
+
+ // number of cycles stalled for I-cache responses
+ Stats::Scalar<> icacheStallCycles;
+ Counter lastIcacheStall;
+
+ // number of cycles stalled for I-cache retries
+ Stats::Scalar<> icacheRetryCycles;
+ Counter lastIcacheRetry;
+
+ // number of cycles stalled for D-cache responses
+ Stats::Scalar<> dcacheStallCycles;
+ Counter lastDcacheStall;
+
+ // number of cycles stalled for D-cache retries
+ Stats::Scalar<> dcacheRetryCycles;
+ Counter lastDcacheRetry;
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+ // These functions are only used in CPU models that split
+ // effective address computation from the actual memory access.
+ void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
+ Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
+
+ void prefetch(Addr addr, unsigned flags)
+ {
+ // need to do this...
+ }
+
+ void writeHint(Addr addr, int size, unsigned flags)
+ {
+ // need to do this...
+ }
+
+ Fault copySrcTranslate(Addr src);
+
+ Fault copy(Addr dest);
+
+ // The register accessor methods provide the index of the
+ // instruction's operand (e.g., 0 or 1), not the architectural
+ // register index, to simplify the implementation of register
+ // renaming. We find the architectural register index by indexing
+ // into the instruction's own operand index table. Note that a
+ // raw pointer to the StaticInst is provided instead of a
+ // ref-counted StaticInstPtr to redice overhead. This is fine as
+ // long as these methods don't copy the pointer into any long-term
+ // storage (which is pretty hard to imagine they would have reason
+ // to do).
+
+ uint64_t readIntReg(const StaticInst *si, int idx)
+ {
+ return cpuXC->readIntReg(si->srcRegIdx(idx));
+ }
+
+ FloatReg readFloatReg(const StaticInst *si, int idx, int width)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatReg(reg_idx, width);
+ }
+
+ FloatReg readFloatReg(const StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatReg(reg_idx);
+ }
+
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatRegBits(reg_idx, width);
+ }
+
+ FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
+ {
+ int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
+ return cpuXC->readFloatRegBits(reg_idx);
+ }
+
+ void setIntReg(const StaticInst *si, int idx, uint64_t val)
+ {
+ cpuXC->setIntReg(si->destRegIdx(idx), val);
+ }
+
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatReg(reg_idx, val, width);
+ }
+
+ void setFloatReg(const StaticInst *si, int idx, FloatReg val)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatReg(reg_idx, val);
+ }
+
+ void setFloatRegBits(const StaticInst *si, int idx,
+ FloatRegBits val, int width)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatRegBits(reg_idx, val, width);
+ }
+
+ void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
+ {
+ int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
+ cpuXC->setFloatRegBits(reg_idx, val);
+ }
+
+ uint64_t readPC() { return cpuXC->readPC(); }
+ uint64_t readNextPC() { return cpuXC->readNextPC(); }
+ uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
+
+ void setPC(uint64_t val) { cpuXC->setPC(val); }
+ void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
+ void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
+
+ MiscReg readMiscReg(int misc_reg)
+ {
+ return cpuXC->readMiscReg(misc_reg);
+ }
+
+ MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
+ {
+ return cpuXC->readMiscRegWithEffect(misc_reg, fault);
+ }
+
+ Fault setMiscReg(int misc_reg, const MiscReg &val)
+ {
+ return cpuXC->setMiscReg(misc_reg, val);
+ }
+
+ Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
+ {
+ return cpuXC->setMiscRegWithEffect(misc_reg, val);
+ }
+
+#if FULL_SYSTEM
+ Fault hwrei() { return cpuXC->hwrei(); }
+ int readIntrFlag() { return cpuXC->readIntrFlag(); }
+ void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
+ bool inPalMode() { return cpuXC->inPalMode(); }
+ void ev5_trap(Fault fault) { fault->invoke(xcProxy); }
+ bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
+#else
+ void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
+#endif
+
+ bool misspeculating() { return cpuXC->misspeculating(); }
+ ExecContext *xcBase() { return xcProxy; }
+};
+
+#endif // __CPU_SIMPLE_BASE_HH__
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
new file mode 100644
index 000000000..70b88c4b1
--- /dev/null
+++ b/src/cpu/simple/timing.cc
@@ -0,0 +1,570 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/utility.hh"
+#include "cpu/exetrace.hh"
+#include "cpu/simple/timing.hh"
+#include "mem/packet_impl.hh"
+#include "sim/builder.hh"
+
+using namespace std;
+using namespace TheISA;
+
+
+void
+TimingSimpleCPU::init()
+{
+ //Create Memory Ports (conect them up)
+ Port *mem_dport = mem->getPort("");
+ dcachePort.setPeer(mem_dport);
+ mem_dport->setPeer(&dcachePort);
+
+ Port *mem_iport = mem->getPort("");
+ icachePort.setPeer(mem_iport);
+ mem_iport->setPeer(&icachePort);
+
+ BaseCPU::init();
+#if FULL_SYSTEM
+ for (int i = 0; i < execContexts.size(); ++i) {
+ ExecContext *xc = execContexts[i];
+
+ // initialize CPU, including PC
+ TheISA::initCPU(xc, xc->readCpuId());
+ }
+#endif
+}
+
+Tick
+TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
+{
+ panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
+ return curTick;
+}
+
+void
+TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
+{
+ panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
+}
+
+void
+TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
+{
+ if (status == RangeChange)
+ return;
+
+ panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
+}
+
+TimingSimpleCPU::TimingSimpleCPU(Params *p)
+ : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
+{
+ _status = Idle;
+ ifetch_pkt = dcache_pkt = NULL;
+}
+
+
+TimingSimpleCPU::~TimingSimpleCPU()
+{
+}
+
+void
+TimingSimpleCPU::serialize(ostream &os)
+{
+ BaseSimpleCPU::serialize(os);
+ SERIALIZE_ENUM(_status);
+}
+
+void
+TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
+{
+ BaseSimpleCPU::unserialize(cp, section);
+ UNSERIALIZE_ENUM(_status);
+}
+
+void
+TimingSimpleCPU::switchOut(Sampler *s)
+{
+ sampler = s;
+ if (status() == Running) {
+ _status = SwitchedOut;
+ }
+ sampler->signalSwitched();
+}
+
+
+void
+TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
+{
+ BaseCPU::takeOverFrom(oldCPU);
+
+ // if any of this CPU's ExecContexts are active, mark the CPU as
+ // running and schedule its tick event.
+ for (int i = 0; i < execContexts.size(); ++i) {
+ ExecContext *xc = execContexts[i];
+ if (xc->status() == ExecContext::Active && _status != Running) {
+ _status = Running;
+ break;
+ }
+ }
+}
+
+
+void
+TimingSimpleCPU::activateContext(int thread_num, int delay)
+{
+ assert(thread_num == 0);
+ assert(cpuXC);
+
+ assert(_status == Idle);
+
+ notIdleFraction++;
+ _status = Running;
+ // kick things off by initiating the fetch of the next instruction
+ Event *e =
+ new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
+ e->schedule(curTick + cycles(delay));
+}
+
+
+void
+TimingSimpleCPU::suspendContext(int thread_num)
+{
+ assert(thread_num == 0);
+ assert(cpuXC);
+
+ panic("TimingSimpleCPU::suspendContext not implemented");
+
+ assert(_status == Running);
+
+ notIdleFraction--;
+ _status = Idle;
+}
+
+
+template <class T>
+Fault
+TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
+{
+ Request *data_read_req = new Request(true);
+
+ data_read_req->setVaddr(addr);
+ data_read_req->setSize(sizeof(T));
+ data_read_req->setFlags(flags);
+ data_read_req->setTime(curTick);
+
+ if (traceData) {
+ traceData->setAddr(data_read_req->getVaddr());
+ }
+
+ // translate to physical address
+ Fault fault = cpuXC->translateDataReadReq(data_read_req);
+
+ // Now do the access.
+ if (fault == NoFault) {
+ Packet *data_read_pkt = new Packet;
+ data_read_pkt->cmd = Read;
+ data_read_pkt->req = data_read_req;
+ data_read_pkt->dataDynamic<T>(new T);
+ data_read_pkt->addr = data_read_req->getPaddr();
+ data_read_pkt->size = sizeof(T);
+ data_read_pkt->dest = Packet::Broadcast;
+
+ if (!dcachePort.sendTiming(data_read_pkt)) {
+ _status = DcacheRetry;
+ dcache_pkt = data_read_pkt;
+ } else {
+ _status = DcacheWaitResponse;
+ dcache_pkt = NULL;
+ }
+ }
+
+ // This will need a new way to tell if it has a dcache attached.
+ if (data_read_req->getFlags() & UNCACHEABLE)
+ recordEvent("Uncached Read");
+
+ return fault;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+
+template
+Fault
+TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
+
+template
+Fault
+TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
+
+template
+Fault
+TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
+
+template
+Fault
+TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
+{
+ return read(addr, *(uint64_t*)&data, flags);
+}
+
+template<>
+Fault
+TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
+{
+ return read(addr, *(uint32_t*)&data, flags);
+}
+
+
+template<>
+Fault
+TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
+{
+ return read(addr, (uint32_t&)data, flags);
+}
+
+
+template <class T>
+Fault
+TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
+{
+ Request *data_write_req = new Request(true);
+ data_write_req->setVaddr(addr);
+ data_write_req->setTime(curTick);
+ data_write_req->setSize(sizeof(T));
+ data_write_req->setFlags(flags);
+
+ // translate to physical address
+ Fault fault = cpuXC->translateDataWriteReq(data_write_req);
+ // Now do the access.
+ if (fault == NoFault) {
+ Packet *data_write_pkt = new Packet;
+ data_write_pkt->cmd = Write;
+ data_write_pkt->req = data_write_req;
+ data_write_pkt->allocate();
+ data_write_pkt->size = sizeof(T);
+ data_write_pkt->set(data);
+ data_write_pkt->addr = data_write_req->getPaddr();
+ data_write_pkt->dest = Packet::Broadcast;
+
+ if (!dcachePort.sendTiming(data_write_pkt)) {
+ _status = DcacheRetry;
+ dcache_pkt = data_write_pkt;
+ } else {
+ _status = DcacheWaitResponse;
+ dcache_pkt = NULL;
+ }
+ }
+
+ // This will need a new way to tell if it's hooked up to a cache or not.
+ if (data_write_req->getFlags() & UNCACHEABLE)
+ recordEvent("Uncached Write");
+
+ // If the write needs to have a fault on the access, consider calling
+ // changeStatus() and changing it to "bad addr write" or something.
+ return fault;
+}
+
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+template
+Fault
+TimingSimpleCPU::write(uint64_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(uint32_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(uint16_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+template
+Fault
+TimingSimpleCPU::write(uint8_t data, Addr addr,
+ unsigned flags, uint64_t *res);
+
+#endif //DOXYGEN_SHOULD_SKIP_THIS
+
+template<>
+Fault
+TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write(*(uint64_t*)&data, addr, flags, res);
+}
+
+template<>
+Fault
+TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write(*(uint32_t*)&data, addr, flags, res);
+}
+
+
+template<>
+Fault
+TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
+{
+ return write((uint32_t)data, addr, flags, res);
+}
+
+
+void
+TimingSimpleCPU::fetch()
+{
+ checkForInterrupts();
+
+ Request *ifetch_req = new Request(true);
+ ifetch_req->setSize(sizeof(MachInst));
+
+ ifetch_pkt = new Packet;
+ ifetch_pkt->cmd = Read;
+ ifetch_pkt->dataStatic(&inst);
+ ifetch_pkt->req = ifetch_req;
+ ifetch_pkt->size = sizeof(MachInst);
+ ifetch_pkt->dest = Packet::Broadcast;
+
+ Fault fault = setupFetchPacket(ifetch_pkt);
+ if (fault == NoFault) {
+ if (!icachePort.sendTiming(ifetch_pkt)) {
+ // Need to wait for retry
+ _status = IcacheRetry;
+ } else {
+ // Need to wait for cache to respond
+ _status = IcacheWaitResponse;
+ // ownership of packet transferred to memory system
+ ifetch_pkt = NULL;
+ }
+ } else {
+ panic("TimingSimpleCPU fetch fault handling not implemented");
+ }
+}
+
+
+void
+TimingSimpleCPU::completeInst(Fault fault)
+{
+ postExecute();
+
+ if (traceData) {
+ traceData->finalize();
+ }
+
+ advancePC(fault);
+
+ if (_status == Running) {
+ // kick off fetch of next instruction... callback from icache
+ // response will cause that instruction to be executed,
+ // keeping the CPU running.
+ fetch();
+ }
+}
+
+
+void
+TimingSimpleCPU::completeIfetch()
+{
+ // received a response from the icache: execute the received
+ // instruction
+ assert(_status == IcacheWaitResponse);
+ _status = Running;
+ preExecute();
+ if (curStaticInst->isMemRef()) {
+ // load or store: just send to dcache
+ Fault fault = curStaticInst->initiateAcc(this, traceData);
+ assert(fault == NoFault);
+ assert(_status == DcacheWaitResponse);
+ // instruction will complete in dcache response callback
+ } else {
+ // non-memory instruction: execute completely now
+ Fault fault = curStaticInst->execute(this, traceData);
+ completeInst(fault);
+ }
+}
+
+
+bool
+TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
+{
+ cpu->completeIfetch();
+ return true;
+}
+
+Packet *
+TimingSimpleCPU::IcachePort::recvRetry()
+{
+ // we shouldn't get a retry unless we have a packet that we're
+ // waiting to transmit
+ assert(cpu->ifetch_pkt != NULL);
+ assert(cpu->_status == IcacheRetry);
+ cpu->_status = IcacheWaitResponse;
+ Packet *tmp = cpu->ifetch_pkt;
+ cpu->ifetch_pkt = NULL;
+ return tmp;
+}
+
+void
+TimingSimpleCPU::completeDataAccess(Packet *pkt)
+{
+ // received a response from the dcache: complete the load or store
+ // instruction
+ assert(pkt->result == Success);
+ assert(_status == DcacheWaitResponse);
+ _status = Running;
+
+ Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
+
+ completeInst(fault);
+}
+
+
+
+bool
+TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
+{
+ cpu->completeDataAccess(pkt);
+ return true;
+}
+
+Packet *
+TimingSimpleCPU::DcachePort::recvRetry()
+{
+ // we shouldn't get a retry unless we have a packet that we're
+ // waiting to transmit
+ assert(cpu->dcache_pkt != NULL);
+ assert(cpu->_status == DcacheRetry);
+ cpu->_status = DcacheWaitResponse;
+ Packet *tmp = cpu->dcache_pkt;
+ cpu->dcache_pkt = NULL;
+ return tmp;
+}
+
+
+////////////////////////////////////////////////////////////////////////
+//
+// TimingSimpleCPU Simulation Object
+//
+BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
+
+ Param<Counter> max_insts_any_thread;
+ Param<Counter> max_insts_all_threads;
+ Param<Counter> max_loads_any_thread;
+ Param<Counter> max_loads_all_threads;
+ SimObjectParam<MemObject *> mem;
+
+#if FULL_SYSTEM
+ SimObjectParam<AlphaITB *> itb;
+ SimObjectParam<AlphaDTB *> dtb;
+ SimObjectParam<System *> system;
+ Param<int> cpu_id;
+ Param<Tick> profile;
+#else
+ SimObjectParam<Process *> workload;
+#endif // FULL_SYSTEM
+
+ Param<int> clock;
+
+ Param<bool> defer_registration;
+ Param<int> width;
+ Param<bool> function_trace;
+ Param<Tick> function_trace_start;
+ Param<bool> simulate_stalls;
+
+END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
+
+BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
+
+ INIT_PARAM(max_insts_any_thread,
+ "terminate when any thread reaches this inst count"),
+ INIT_PARAM(max_insts_all_threads,
+ "terminate when all threads have reached this inst count"),
+ INIT_PARAM(max_loads_any_thread,
+ "terminate when any thread reaches this load count"),
+ INIT_PARAM(max_loads_all_threads,
+ "terminate when all threads have reached this load count"),
+ INIT_PARAM(mem, "memory"),
+
+#if FULL_SYSTEM
+ INIT_PARAM(itb, "Instruction TLB"),
+ INIT_PARAM(dtb, "Data TLB"),
+ INIT_PARAM(system, "system object"),
+ INIT_PARAM(cpu_id, "processor ID"),
+ INIT_PARAM(profile, ""),
+#else
+ INIT_PARAM(workload, "processes to run"),
+#endif // FULL_SYSTEM
+
+ INIT_PARAM(clock, "clock speed"),
+ INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
+ INIT_PARAM(width, "cpu width"),
+ INIT_PARAM(function_trace, "Enable function trace"),
+ INIT_PARAM(function_trace_start, "Cycle to start function trace"),
+ INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
+
+END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
+
+
+CREATE_SIM_OBJECT(TimingSimpleCPU)
+{
+ TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
+ params->name = getInstanceName();
+ params->numberOfThreads = 1;
+ params->max_insts_any_thread = max_insts_any_thread;
+ params->max_insts_all_threads = max_insts_all_threads;
+ params->max_loads_any_thread = max_loads_any_thread;
+ params->max_loads_all_threads = max_loads_all_threads;
+ params->deferRegistration = defer_registration;
+ params->clock = clock;
+ params->functionTrace = function_trace;
+ params->functionTraceStart = function_trace_start;
+ params->mem = mem;
+
+#if FULL_SYSTEM
+ params->itb = itb;
+ params->dtb = dtb;
+ params->system = system;
+ params->cpu_id = cpu_id;
+ params->profile = profile;
+#else
+ params->process = workload;
+#endif
+
+ TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
+ return cpu;
+}
+
+REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
+
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
new file mode 100644
index 000000000..83be025d9
--- /dev/null
+++ b/src/cpu/simple/timing.hh
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CPU_SIMPLE_TIMING_HH__
+#define __CPU_SIMPLE_TIMING_HH__
+
+#include "cpu/simple/base.hh"
+
+class TimingSimpleCPU : public BaseSimpleCPU
+{
+ public:
+
+ struct Params : public BaseSimpleCPU::Params {
+ };
+
+ TimingSimpleCPU(Params *params);
+ virtual ~TimingSimpleCPU();
+
+ virtual void init();
+
+ public:
+ //
+ enum Status {
+ Idle,
+ Running,
+ IcacheRetry,
+ IcacheWaitResponse,
+ IcacheWaitSwitch,
+ DcacheRetry,
+ DcacheWaitResponse,
+ DcacheWaitSwitch,
+ SwitchedOut
+ };
+
+ protected:
+ Status _status;
+
+ Status status() const { return _status; }
+
+ private:
+
+ class CpuPort : public Port
+ {
+ protected:
+ TimingSimpleCPU *cpu;
+
+ public:
+
+ CpuPort(TimingSimpleCPU *_cpu)
+ : cpu(_cpu)
+ { }
+
+ protected:
+
+ virtual Tick recvAtomic(Packet *pkt);
+
+ virtual void recvFunctional(Packet *pkt);
+
+ virtual void recvStatusChange(Status status);
+
+ virtual void getDeviceAddressRanges(AddrRangeList &resp,
+ AddrRangeList &snoop)
+ { resp.clear(); snoop.clear(); }
+ };
+
+ class IcachePort : public CpuPort
+ {
+ public:
+
+ IcachePort(TimingSimpleCPU *_cpu)
+ : CpuPort(_cpu)
+ { }
+
+ protected:
+
+ virtual bool recvTiming(Packet *pkt);
+
+ virtual Packet *recvRetry();
+ };
+
+ class DcachePort : public CpuPort
+ {
+ public:
+
+ DcachePort(TimingSimpleCPU *_cpu)
+ : CpuPort(_cpu)
+ { }
+
+ protected:
+
+ virtual bool recvTiming(Packet *pkt);
+
+ virtual Packet *recvRetry();
+ };
+
+ IcachePort icachePort;
+ DcachePort dcachePort;
+
+ Packet *ifetch_pkt;
+ Packet *dcache_pkt;
+
+ public:
+
+ virtual void serialize(std::ostream &os);
+ virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+ void switchOut(Sampler *s);
+ void takeOverFrom(BaseCPU *oldCPU);
+
+ virtual void activateContext(int thread_num, int delay);
+ virtual void suspendContext(int thread_num);
+
+ template <class T>
+ Fault read(Addr addr, T &data, unsigned flags);
+
+ template <class T>
+ Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
+
+ void fetch();
+ void completeInst(Fault fault);
+ void completeIfetch();
+ void completeDataAccess(Packet *);
+};
+
+#endif // __CPU_SIMPLE_TIMING_HH__
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