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authorRon Dreslinski <rdreslin@umich.edu>2006-11-17 21:55:28 -0500
committerRon Dreslinski <rdreslin@umich.edu>2006-11-17 21:55:28 -0500
commitcd0b65508e3f9d9f72cd834aeccf9fd1f0349351 (patch)
treee92d97d22335627754de60a808183e2d00ea3c9c /src/cpu/simple
parentdbdf2f14ae6b586efd31b73aa4548a38ecee263f (diff)
downloadgem5-cd0b65508e3f9d9f72cd834aeccf9fd1f0349351.tar.xz
Make an initialization pass for the thread context and set the [phys,virt]Port correctly
src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Call the thread context initialization --HG-- extra : convert_revision : d7dc2a8b893dc670077b7f6150d4b710a1778620
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc3
-rw-r--r--src/cpu/simple/timing.cc3
2 files changed, 6 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 133b5500b..cd335e36d 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -77,6 +77,9 @@ AtomicSimpleCPU::init()
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
+ // initialize the mem pointers
+ tc->init();
+
// initialize CPU, including PC
TheISA::initCPU(tc, tc->readCpuId());
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 3648f7613..aa23a00e8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -59,6 +59,9 @@ TimingSimpleCPU::init()
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
+ // initialize the mem pointers
+ tc->init();
+
// initialize CPU, including PC
TheISA::initCPU(tc, tc->readCpuId());
}