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authorGabe Black <gblack@eecs.umich.edu>2007-03-13 16:13:21 +0000
committerGabe Black <gblack@eecs.umich.edu>2007-03-13 16:13:21 +0000
commitce18d900a17cdda2cc041b51c56e6c84fb155331 (patch)
treed7be0cac19e550c93fc207e749ea80e1cf9a639e /src/cpu/simple
parent8edc9d79cee3edd6d16a8254a0180aaa242974c7 (diff)
downloadgem5-ce18d900a17cdda2cc041b51c56e6c84fb155331.tar.xz
Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha. Started implementing the x86 predecoder. --HG-- extra : convert_revision : a13ea257c8943ef25e9bc573024a99abacf4a70d
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/base.cc40
-rw-r--r--src/cpu/simple/base.hh6
2 files changed, 25 insertions, 21 deletions
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f6c109127..c27be02bf 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -367,18 +367,18 @@ BaseSimpleCPU::preExecute()
inst = gtoh(inst);
//If we're not in the middle of a macro instruction
if (!curMacroStaticInst) {
-#if THE_ISA == ALPHA_ISA
- StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->readPC()));
-#elif THE_ISA == SPARC_ISA
- StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
-#elif THE_ISA == X86_ISA
- StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
-#elif THE_ISA == MIPS_ISA
- //Mips doesn't do anything in it's MakeExtMI function right now,
- //so it won't be called.
- StaticInstPtr instPtr = StaticInst::decode(inst);
-#endif
- if (instPtr->isMacroOp()) {
+ StaticInstPtr instPtr = NULL;
+
+ //Predecode, ie bundle up an ExtMachInst
+ unsigned int result =
+ predecode(extMachInst, thread->readPC(), inst, thread->getTC());
+ //If an instruction is ready, decode it
+ if (result & ExtMIReady)
+ instPtr = StaticInst::decode(extMachInst);
+
+ //If we decoded an instruction and it's microcoded, start pulling
+ //out micro ops
+ if (instPtr && instPtr->isMacroOp()) {
curMacroStaticInst = instPtr;
curStaticInst = curMacroStaticInst->
fetchMicroOp(thread->readMicroPC());
@@ -391,17 +391,19 @@ BaseSimpleCPU::preExecute()
fetchMicroOp(thread->readMicroPC());
}
+ //If we decoded an instruction this "tick", record information about it.
+ if(curStaticInst)
+ {
+ traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
+ thread->readPC());
- traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
- thread->readPC());
-
- DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
- curStaticInst->getName(), curStaticInst->getOpcode(),
- curStaticInst->machInst);
+ DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
+ curStaticInst->getName(), curStaticInst->machInst);
#if FULL_SYSTEM
- thread->setInst(inst);
+ thread->setInst(inst);
#endif // FULL_SYSTEM
+ }
}
void
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 980ea2f96..10787c474 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -74,7 +74,6 @@ namespace Trace {
class BaseSimpleCPU : public BaseCPU
{
protected:
- typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
typedef TheISA::FloatReg FloatReg;
typedef TheISA::FloatRegBits FloatRegBits;
@@ -122,7 +121,10 @@ class BaseSimpleCPU : public BaseCPU
#endif
// current instruction
- MachInst inst;
+ TheISA::MachInst inst;
+
+ // current extended machine instruction
+ TheISA::ExtMachInst extMachInst;
// Static data storage
TheISA::LargestRead dataReg;