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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
commit6bed6e0352a68723ea55017b3e09a8c279af11ec (patch)
treef7fb2a163ea470144a424bf21a7dd578754546af /src/cpu/simple
parentd3444c6603afe38b00036292a854f52069b90a80 (diff)
downloadgem5-6bed6e0352a68723ea55017b3e09a8c279af11ec.tar.xz
cpu: Add CPU support for generatig wake up events when LLSC adresses are snooped.
This patch add support for generating wake-up events in the CPU when an address that is currently in the exclusive state is hit by a snoop. This mechanism is required for ARMv8 multi-processor support.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc34
-rw-r--r--src/cpu/simple/atomic.hh33
-rw-r--r--src/cpu/simple/timing.cc12
-rw-r--r--src/cpu/simple/timing.hh12
4 files changed, 77 insertions, 14 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 617e845a5..b1efbc5ce 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2012 ARM Limited
+ * Copyright (c) 2012-2013 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
@@ -278,6 +278,36 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num)
}
+Tick
+AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt)
+{
+ DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
+ pkt->cmdString());
+
+ // if snoop invalidates, release any associated locks
+ if (pkt->isInvalidate()) {
+ DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
+ pkt->getAddr());
+ TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
+ }
+
+ return 0;
+}
+
+void
+AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt)
+{
+ DPRINTF(SimpleCPU, "received snoop pkt for addr:%#x %s\n", pkt->getAddr(),
+ pkt->cmdString());
+
+ // if snoop invalidates, release any associated locks
+ if (pkt->isInvalidate()) {
+ DPRINTF(SimpleCPU, "received invalidation for addr:%#x\n",
+ pkt->getAddr());
+ TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
+ }
+}
+
Fault
AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
unsigned size, unsigned flags)
@@ -402,7 +432,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
if (req->isLLSC()) {
cmd = MemCmd::StoreCondReq;
- do_access = TheISA::handleLockedWrite(thread, req);
+ do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
} else if (req->isSwap()) {
cmd = MemCmd::SwapReq;
if (req->isCondSwap()) {
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 7366213f8..7426139e7 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -147,17 +147,12 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
- AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
+ AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
: MasterPort(_name, _cpu)
{ }
protected:
-
- virtual Tick recvAtomicSnoop(PacketPtr pkt)
- {
- // Snooping a coherence request, just return
- return 0;
- }
+ virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
bool recvTimingResp(PacketPtr pkt)
{
@@ -172,8 +167,30 @@ class AtomicSimpleCPU : public BaseSimpleCPU
};
+ class AtomicCPUDPort : public AtomicCPUPort
+ {
+
+ public:
+
+ AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
+ : AtomicCPUPort(_name, _cpu), cpu(_cpu)
+ {
+ cacheBlockMask = ~(cpu->cacheLineSize() - 1);
+ }
+
+ bool isSnooping() const { return true; }
+
+ Addr cacheBlockMask;
+ protected:
+ BaseSimpleCPU *cpu;
+
+ virtual Tick recvAtomicSnoop(PacketPtr pkt);
+ virtual void recvFunctionalSnoop(PacketPtr pkt);
+ };
+
+
AtomicCPUPort icachePort;
- AtomicCPUPort dcachePort;
+ AtomicCPUDPort dcachePort;
bool fastmem;
Request ifetch_req;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 7996a6ddd..366164e36 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012 ARM Limited
+ * Copyright (c) 2010-2013 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -96,6 +96,7 @@ TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
}
+
TimingSimpleCPU::~TimingSimpleCPU()
{
}
@@ -273,7 +274,7 @@ TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
bool do_access = true; // flag to suppress cache access
if (req->isLLSC()) {
- do_access = TheISA::handleLockedWrite(thread, req);
+ do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
} else if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
@@ -813,6 +814,13 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
advanceInst(fault);
}
+void
+TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
+{
+ TheISA::handleLockedSnoop(cpu->thread, pkt, cacheBlockMask);
+}
+
+
bool
TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
{
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 03264315e..4a5a20429 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -165,7 +165,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
/**
* Snooping a coherence request, do nothing.
*/
- virtual void recvTimingSnoopReq(PacketPtr pkt) { }
+ virtual void recvTimingSnoopReq(PacketPtr pkt) {}
TimingSimpleCPU* cpu;
@@ -217,10 +217,18 @@ class TimingSimpleCPU : public BaseSimpleCPU
DcachePort(TimingSimpleCPU *_cpu)
: TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
tickEvent(_cpu)
- { }
+ {
+ cacheBlockMask = ~(cpu->cacheLineSize() - 1);
+ }
+ Addr cacheBlockMask;
protected:
+ /** Snoop a coherence request, we need to check if this causes
+ * a wakeup event on a cpu that is monitoring an address
+ */
+ virtual void recvTimingSnoopReq(PacketPtr pkt);
+
virtual bool recvTimingResp(PacketPtr pkt);
virtual void recvRetry();