misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.

5 files changed, 47 insertions, 51 deletions

diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 2bea12ab2..372df7cbd 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -191,8 +191,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
   public:
 
-    DrainState drain() M5_ATTR_OVERRIDE;
-    void drainResume() M5_ATTR_OVERRIDE;
+    DrainState drain() override;
+    void drainResume() override;
 
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 1fcd5c203..72ac9bb4b 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -93,7 +93,7 @@ class BaseSimpleCPU : public BaseCPU
   public:
     BaseSimpleCPU(BaseSimpleCPUParams *params);
     virtual ~BaseSimpleCPU();
-    void wakeup(ThreadID tid) M5_ATTR_OVERRIDE;
+    void wakeup(ThreadID tid) override;
     virtual void init();
   public:
     Trace::InstRecord *traceData;
@@ -152,9 +152,8 @@ class BaseSimpleCPU : public BaseCPU
     virtual Counter totalInsts() const;
     virtual Counter totalOps() const;
 
-    void serializeThread(CheckpointOut &cp,
-                         ThreadID tid) const M5_ATTR_OVERRIDE;
-    void unserializeThread(CheckpointIn &cp, ThreadID tid) M5_ATTR_OVERRIDE;
+    void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
+    void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 
 };
 
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 591cf8227..43a012404 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -160,23 +160,21 @@ class SimpleExecContext : public ExecContext {
     { }
 
     /** Reads an integer register. */
-    IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+    IntReg readIntRegOperand(const StaticInst *si, int idx) override
     {
         numIntRegReads++;
         return thread->readIntReg(si->srcRegIdx(idx));
     }
 
     /** Sets an integer register to a value. */
-    void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
-        M5_ATTR_OVERRIDE
+    void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
     {
         numIntRegWrites++;
         thread->setIntReg(si->destRegIdx(idx), val);
     }
 
     /** Reads a floating point register of single register width. */
-    FloatReg readFloatRegOperand(const StaticInst *si, int idx)
-        M5_ATTR_OVERRIDE
+    FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
     {
         numFpRegReads++;
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
@@ -185,8 +183,7 @@ class SimpleExecContext : public ExecContext {
 
     /** Reads a floating point register in its binary format, instead
      * of by value. */
-    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
-        M5_ATTR_OVERRIDE
+    FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
     {
         numFpRegReads++;
         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
@@ -194,8 +191,8 @@ class SimpleExecContext : public ExecContext {
     }
 
     /** Sets a floating point register of single width to a value. */
-    void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
-        M5_ATTR_OVERRIDE
+    void setFloatRegOperand(const StaticInst *si, int idx,
+                            FloatReg val) override
     {
         numFpRegWrites++;
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
@@ -205,37 +202,36 @@ class SimpleExecContext : public ExecContext {
     /** Sets the bits of a floating point register of single width
      * to a binary value. */
     void setFloatRegOperandBits(const StaticInst *si, int idx,
-                                FloatRegBits val) M5_ATTR_OVERRIDE
+                                FloatRegBits val) override
     {
         numFpRegWrites++;
         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
         thread->setFloatRegBits(reg_idx, val);
     }
 
-    CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+    CCReg readCCRegOperand(const StaticInst *si, int idx) override
     {
         numCCRegReads++;
         int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
         return thread->readCCReg(reg_idx);
     }
 
-    void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
-        M5_ATTR_OVERRIDE
+    void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
     {
         numCCRegWrites++;
         int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
         thread->setCCReg(reg_idx, val);
     }
 
-    MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
+    MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
     {
         numIntRegReads++;
         int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
         return thread->readMiscReg(reg_idx);
     }
 
-    void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
-        M5_ATTR_OVERRIDE
+    void setMiscRegOperand(const StaticInst *si, int idx,
+                           const MiscReg &val) override
     {
         numIntRegWrites++;
         int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
@@ -246,7 +242,7 @@ class SimpleExecContext : public ExecContext {
      * Reads a miscellaneous register, handling any architectural
      * side effects due to reading that register.
      */
-    MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE
+    MiscReg readMiscReg(int misc_reg) override
     {
         numIntRegReads++;
         return thread->readMiscReg(misc_reg);
@@ -256,18 +252,18 @@ class SimpleExecContext : public ExecContext {
      * Sets a miscellaneous register, handling any architectural
      * side effects due to writing that register.
      */
-    void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE
+    void setMiscReg(int misc_reg, const MiscReg &val) override
     {
         numIntRegWrites++;
         thread->setMiscReg(misc_reg, val);
     }
 
-    PCState pcState() const M5_ATTR_OVERRIDE
+    PCState pcState() const override
     {
         return thread->pcState();
     }
 
-    void pcState(const PCState &val) M5_ATTR_OVERRIDE
+    void pcState(const PCState &val) override
     {
         thread->pcState(val);
     }
@@ -278,7 +274,7 @@ class SimpleExecContext : public ExecContext {
      *
      * @note Only valid for memory ops.
      */
-    void setEA(Addr EA) M5_ATTR_OVERRIDE
+    void setEA(Addr EA) override
     { panic("BaseSimpleCPU::setEA() not implemented\n"); }
 
     /**
@@ -286,17 +282,17 @@ class SimpleExecContext : public ExecContext {
      *
      * @note Only valid for memory ops.
      */
-    Addr getEA() const M5_ATTR_OVERRIDE
+    Addr getEA() const override
     { panic("BaseSimpleCPU::getEA() not implemented\n"); }
 
     Fault readMem(Addr addr, uint8_t *data, unsigned int size,
-                  unsigned int flags) M5_ATTR_OVERRIDE
+                  unsigned int flags) override
     {
         return cpu->readMem(addr, data, size, flags);
     }
 
     Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
-                   unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE
+                   unsigned int flags, uint64_t *res) override
     {
         return cpu->writeMem(data, size, addr, flags, res);
     }
@@ -304,7 +300,7 @@ class SimpleExecContext : public ExecContext {
     /**
      * Sets the number of consecutive store conditional failures.
      */
-    void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE
+    void setStCondFailures(unsigned int sc_failures) override
     {
         thread->setStCondFailures(sc_failures);
     }
@@ -312,7 +308,7 @@ class SimpleExecContext : public ExecContext {
     /**
      * Returns the number of consecutive store conditional failures.
      */
-    unsigned int readStCondFailures() const M5_ATTR_OVERRIDE
+    unsigned int readStCondFailures() const override
     {
         return thread->readStCondFailures();
     }
@@ -320,7 +316,7 @@ class SimpleExecContext : public ExecContext {
     /**
      * Executes a syscall specified by the callnum.
      */
-    void syscall(int64_t callnum) M5_ATTR_OVERRIDE
+    void syscall(int64_t callnum) override
     {
         if (FullSystem)
             panic("Syscall emulation isn't available in FS mode.");
@@ -329,7 +325,7 @@ class SimpleExecContext : public ExecContext {
     }
 
     /** Returns a pointer to the ThreadContext. */
-    ThreadContext *tcBase() M5_ATTR_OVERRIDE
+    ThreadContext *tcBase() override
     {
         return thread->getTC();
     }
@@ -338,7 +334,7 @@ class SimpleExecContext : public ExecContext {
      * Somewhat Alpha-specific function that handles returning from an
      * error or interrupt.
      */
-    Fault hwrei() M5_ATTR_OVERRIDE
+    Fault hwrei() override
     {
         return thread->hwrei();
     }
@@ -347,17 +343,17 @@ class SimpleExecContext : public ExecContext {
      * Check for special simulator handling of specific PAL calls.  If
      * return value is false, actual PAL call will be suppressed.
      */
-    bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE
+    bool simPalCheck(int palFunc) override
     {
         return thread->simPalCheck(palFunc);
     }
 
-    bool readPredicate() M5_ATTR_OVERRIDE
+    bool readPredicate() override
     {
         return thread->readPredicate();
     }
 
-    void setPredicate(bool val) M5_ATTR_OVERRIDE
+    void setPredicate(bool val) override
     {
         thread->setPredicate(val);
 
@@ -369,41 +365,41 @@ class SimpleExecContext : public ExecContext {
     /**
      * Invalidate a page in the DTLB <i>and</i> ITLB.
      */
-    void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
+    void demapPage(Addr vaddr, uint64_t asn) override
     {
         thread->demapPage(vaddr, asn);
     }
 
-    void armMonitor(Addr address) M5_ATTR_OVERRIDE
+    void armMonitor(Addr address) override
     {
         cpu->armMonitor(thread->threadId(), address);
     }
 
-    bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
+    bool mwait(PacketPtr pkt) override
     {
         return cpu->mwait(thread->threadId(), pkt);
     }
 
-    void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
+    void mwaitAtomic(ThreadContext *tc) override
     {
         cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
     }
 
-    AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
+    AddressMonitor *getAddrMonitor() override
     {
         return cpu->getCpuAddrMonitor(thread->threadId());
     }
 
 #if THE_ISA == MIPS_ISA
     MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
-        M5_ATTR_OVERRIDE
+        override
     {
         panic("Simple CPU models do not support multithreaded "
               "register access.");
     }
 
     void setRegOtherThread(int regIdx, MiscReg val,
-                           ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE
+                           ThreadID tid = InvalidThreadID) override
     {
         panic("Simple CPU models do not support multithreaded "
               "register access.");
diff --git a/src/cpu/simple/probes/simpoint.hh b/src/cpu/simple/probes/simpoint.hh
index e2c343755..2f4ed080d 100644
--- a/src/cpu/simple/probes/simpoint.hh
+++ b/src/cpu/simple/probes/simpoint.hh
@@ -41,7 +41,8 @@
 #ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
 #define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
 
-#include "base/hashmap.hh"
+#include <unordered_map>
+
 #include "cpu/simple_thread.hh"
 #include "params/SimPoint.hh"
 #include "sim/probe/probe.hh"
@@ -59,7 +60,7 @@
 typedef std::pair<Addr, Addr> BasicBlockRange;
 
 /** Overload hash function for BasicBlockRange type */
-__hash_namespace_begin
+namespace std {
 template <>
 struct hash<BasicBlockRange>
 {
@@ -68,7 +69,7 @@ struct hash<BasicBlockRange>
         return hash<Addr>()(bb.first + bb.second);
     }
 };
-__hash_namespace_end
+}
 
 class SimPoint : public ProbeListenerObject
 {
@@ -109,7 +110,7 @@ class SimPoint : public ProbeListenerObject
     };
 
     /** Hash table containing all previously seen basic blocks */
-    m5::hash_map<BasicBlockRange, BBInfo> bbMap;
+    std::unordered_map<BasicBlockRange, BBInfo> bbMap;
     /** Currently executing basic block */
     BasicBlockRange currentBBV;
     /** inst count in current basic block */
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index f1cc09e42..a6c7df988 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -272,8 +272,8 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
   public:
 
-    DrainState drain() M5_ATTR_OVERRIDE;
-    void drainResume() M5_ATTR_OVERRIDE;
+    DrainState drain() override;
+    void drainResume() override;
 
     void switchOut();
     void takeOverFrom(BaseCPU *oldCPU);