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authorRon Dreslinski <rdreslin@umich.edu>2006-07-07 15:16:41 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-07-07 15:16:41 -0400
commit76c110d924d2adfa209ad4302af791dfe6f67946 (patch)
tree7df6d5bbf7d76a6250a4bc1c41ce4fc35024575b /src/cpu/simple
parentea11c7bdbefc8eb640f875cdf91a6d6bed398ec4 (diff)
downloadgem5-76c110d924d2adfa209ad4302af791dfe6f67946.tar.xz
Remove hack now that ports work properly
--HG-- extra : convert_revision : 43c22294867d7cbbc67ae66ec41a1d1c89f5a59d
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/timing.cc7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 170c78d3a..12a47fb3e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -452,12 +452,7 @@ TimingSimpleCPU::completeIfetch(Packet *pkt)
bool
TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
{
- if (cpu->_status == DcacheWaitResponse)
- cpu->completeDataAccess(pkt);
- else if (cpu->_status == IcacheWaitResponse)
- cpu->completeIfetch(pkt);
- else
- assert("OOPS" && 0);
+ cpu->completeIfetch(pkt);
return true;
}