alpha,arm,mips,power,x86,cpu,sim: Cleanup activate/deactivate

activate(), suspend(), and halt() used on thread contexts had an optional
delay parameter. However this parameter was often ignored. Also, when used,
the delay was seemily arbitrarily set to 0 or 1 cycle (no other delays were
ever specified). This patch removes the delay parameter and 'Events'
associated with them across all ISAs and cores. Unused activate logic
is also removed.

4 files changed, 8 insertions, 8 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 0ac4a5495..5af3854e7 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -222,9 +222,9 @@ AtomicSimpleCPU::verifyMemoryMode() const
 }
 
 void
-AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
+AtomicSimpleCPU::activateContext(ThreadID thread_num)
 {
-    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
+    DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
 
     assert(thread_num == 0);
     assert(thread);
@@ -236,7 +236,7 @@ AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
     numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend);
 
     //Make sure ticks are still on multiples of cycles
-    schedule(tickEvent, clockEdge(delay));
+    schedule(tickEvent, clockEdge(Cycles(0)));
     _status = BaseSimpleCPU::Running;
 }
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 91f558e06..a2f3927b4 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -200,7 +200,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
     void verifyMemoryMode() const;
 
-    virtual void activateContext(ThreadID thread_num, Cycles delay);
+    virtual void activateContext(ThreadID thread_num);
     virtual void suspendContext(ThreadID thread_num);
 
     Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9c8f8b57a..9a9714bee 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -200,9 +200,9 @@ TimingSimpleCPU::verifyMemoryMode() const
 }
 
 void
-TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
+TimingSimpleCPU::activateContext(ThreadID thread_num)
 {
-    DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
+    DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
 
     assert(thread_num == 0);
     assert(thread);
@@ -213,7 +213,7 @@ TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
     _status = BaseSimpleCPU::Running;
 
     // kick things off by initiating the fetch of the next instruction
-    schedule(fetchEvent, clockEdge(delay));
+    schedule(fetchEvent, clockEdge(Cycles(0)));
 }
 
 
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index a7ea57c67..24f7002ff 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -271,7 +271,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
     void verifyMemoryMode() const;
 
-    virtual void activateContext(ThreadID thread_num, Cycles delay);
+    virtual void activateContext(ThreadID thread_num);
     virtual void suspendContext(ThreadID thread_num);
 
     Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);