Add base ARM code to M5

--HG--
extra : convert_revision : d811bf87d1a0bfc712942ecd3db1b48fc75257af

1 files changed, 10 insertions, 4 deletions

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fc35f2666..e1fc6882f 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
             assert(fault == NoFault);
         } else {
             if (fault == NoFault) {
+                // Note that ARM can have NULL packets if the instruction gets
+                // squashed due to predication
                 // early fail on store conditional: complete now
-                assert(dcache_pkt != NULL);
+                assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
+
                 fault = curStaticInst->completeAcc(dcache_pkt, this,
                                                    traceData);
-                delete dcache_pkt->req;
-                delete dcache_pkt;
-                dcache_pkt = NULL;
+                if (dcache_pkt != NULL)
+                {
+                    delete dcache_pkt->req;
+                    delete dcache_pkt;
+                    dcache_pkt = NULL;
+                }
 
                 // keep an instruction count
                 if (fault == NoFault)