diff options
| author | Lena Olson <lena@cs.wisc,edu> | 2013-08-19 03:52:35 -0400 |
|---|---|---|
| committer | Lena Olson <lena@cs.wisc,edu> | 2013-08-19 03:52:35 -0400 |
| commit | 646c4a23ca44aab5468c896034288151c89be782 (patch) | |
| tree | e63c57a515669a9c7c24b39b8cfcf39804d00276 /src/cpu/simple | |
| parent | c26911013c799d63dfe854de8cce11137324cde2 (diff) | |
| download | gem5-646c4a23ca44aab5468c896034288151c89be782.tar.xz | |
cpu: Accurately count idle cycles for simple cpu
Added a couple missing updates to the notIdleFraction stat. Without
these, it sometimes gives a (not) idle fraction that is greater than 1
or less than 0.
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 6 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 6 |
2 files changed, 8 insertions, 4 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index ffd1c4d43..d29903c2f 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -175,8 +175,10 @@ AtomicSimpleCPU::drainResume() if (thread->status() == ThreadContext::Active) { schedule(tickEvent, nextCycle()); _status = BaseSimpleCPU::Running; + notIdleFraction = 1; } else { _status = BaseSimpleCPU::Idle; + notIdleFraction = 0; } system->totalNumInsts = 0; @@ -244,7 +246,7 @@ AtomicSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) assert(_status == Idle); assert(!tickEvent.scheduled()); - notIdleFraction++; + notIdleFraction = 1; numCycles += ticksToCycles(thread->lastActivate - thread->lastSuspend); //Make sure ticks are still on multiples of cycles @@ -271,7 +273,7 @@ AtomicSimpleCPU::suspendContext(ThreadID thread_num) if (tickEvent.scheduled()) deschedule(tickEvent); - notIdleFraction--; + notIdleFraction = 0; _status = Idle; } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 075d05d81..744bf8397 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -143,8 +143,10 @@ TimingSimpleCPU::drainResume() if (thread->status() == ThreadContext::Active) { schedule(fetchEvent, nextCycle()); _status = BaseSimpleCPU::Running; + notIdleFraction = 1; } else { _status = BaseSimpleCPU::Idle; + notIdleFraction = 0; } } @@ -206,7 +208,7 @@ TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay) assert(_status == Idle); - notIdleFraction++; + notIdleFraction = 1; _status = BaseSimpleCPU::Running; // kick things off by initiating the fetch of the next instruction @@ -230,7 +232,7 @@ TimingSimpleCPU::suspendContext(ThreadID thread_num) // just change status to Idle... if status != Running, // completeInst() will not initiate fetch of next instruction. - notIdleFraction--; + notIdleFraction = 0; _status = Idle; } |