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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-04-08 22:21:27 -0700 |
| commit | 7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60 (patch) | |
| tree | 4c212f665de2628eac6f84d389de7a79b6d0b933 /src/cpu/simple | |
| parent | 08043c777f1f05f5e14581950013461f328965be (diff) | |
| download | gem5-7b5a96f06b530db35637aca6f9d0f7a2ddfa6e60.tar.xz | |
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 2 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 6 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 17f93c882..b5e65265a 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -609,7 +609,7 @@ AtomicSimpleCPU::tick() bool fromRom = isRomMicroPC(thread->readMicroPC()); if (!fromRom && !curMacroStaticInst) { setupFetchRequest(&ifetch_req); - fault = thread->itb->translateAtomic(&ifetch_req, tc); + fault = thread->itb->translateAtomic(&ifetch_req, tc, false, true); } if (fault == NoFault) { diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index a8f86f8d2..874eeefb7 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -672,7 +672,7 @@ TimingSimpleCPU::fetch() ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); setupFetchRequest(ifetch_req); thread->itb->translateTiming(ifetch_req, tc, - &fetchTranslation); + &fetchTranslation, false, true); } else { _status = IcacheWaitResponse; completeIfetch(NULL); diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index a02ec48c9..731eeeefc 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -106,7 +106,7 @@ class TimingSimpleCPU : public BaseSimpleCPU {} void finish(Fault fault, RequestPtr req, - ThreadContext *tc, bool write) + ThreadContext *tc, bool write, bool execute) { cpu->sendFetch(fault, req, tc); } @@ -129,7 +129,7 @@ class TimingSimpleCPU : public BaseSimpleCPU void finish(Fault fault, RequestPtr req, - ThreadContext *tc, bool write) + ThreadContext *tc, bool write, bool execute) { cpu->sendData(fault, req, data, res, read); delete this; @@ -173,7 +173,7 @@ class TimingSimpleCPU : public BaseSimpleCPU void finish(Fault fault, RequestPtr req, - ThreadContext *tc, bool write) + ThreadContext *tc, bool write, bool execute) { assert(state); assert(state->outstanding); |