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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-02-15 17:40:08 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-02-15 17:40:08 -0500 |
commit | 7cd1fd4324bc1f465a9f96a447d240ab697febd2 (patch) | |
tree | 5a18cd552a6258b732afd7c09f143130df25f157 /src/cpu/simple | |
parent | db5c478e707ba5c7ffe8713ece5534924208500a (diff) | |
download | gem5-7cd1fd4324bc1f465a9f96a447d240ab697febd2.tar.xz |
cpu: Add CPU metadata om the Python classes
The configuration scripts currently hard-code the requirements of each
CPU. This is clearly not optimal as it makes writing new configuration
scripts painful and adding new CPU models requires existing scripts to
be updated. This patch adds the following class methods to the base
CPU and all relevant CPUs:
* memory_mode -- Return a string describing the current memory mode
(invalid/atomic/timing).
* require_caches -- Does the CPU model require caches?
* support_take_over -- Does the CPU support CPU handover?
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/AtomicSimpleCPU.py | 13 | ||||
-rw-r--r-- | src/cpu/simple/TimingSimpleCPU.py | 8 |
2 files changed, 21 insertions, 0 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py index 1927a5862..c747582f6 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/AtomicSimpleCPU.py @@ -42,8 +42,21 @@ from m5.params import * from BaseSimpleCPU import BaseSimpleCPU class AtomicSimpleCPU(BaseSimpleCPU): + """Simple CPU model executing a configurable number of + instructions per cycle. This model uses the simplified 'atomic' + memory mode.""" + type = 'AtomicSimpleCPU' cxx_header = "cpu/simple/atomic.hh" + + @classmethod + def memory_mode(cls): + return 'atomic' + + @classmethod + def support_take_over(cls): + return True + width = Param.Int(1, "CPU width") simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles") simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles") diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py index 72560366e..25149eaa8 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/TimingSimpleCPU.py @@ -32,3 +32,11 @@ from BaseSimpleCPU import BaseSimpleCPU class TimingSimpleCPU(BaseSimpleCPU): type = 'TimingSimpleCPU' cxx_header = "cpu/simple/timing.hh" + + @classmethod + def memory_mode(cls): + return 'timing' + + @classmethod + def support_take_over(cls): + return True |