CPU: Get rid of translate... functions from various interface classes.

5 files changed, 53 insertions, 195 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index feb8a7fc5..cd07a9fe3 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -314,7 +314,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
+        Fault fault = thread->dtb->translate(req, tc, false);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -370,61 +370,6 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
     }
 }
 
-Fault
-AtomicSimpleCPU::translateDataReadAddr(Addr vaddr, Addr & paddr,
-        int size, unsigned flags)
-{
-    // use the CPU's statically allocated read request and packet objects
-    Request *req = &data_read_req;
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    //The block size of our peer.
-    int blockSize = dcachePort.peerBlockSize();
-    //The size of the data we're trying to read.
-    int dataSize = size;
-
-    bool firstTimeThrough = true;
-
-    //The address of the second part of this access if it needs to be split
-    //across a cache line boundary.
-    Addr secondAddr = roundDown(vaddr + dataSize - 1, blockSize);
-
-    if(secondAddr > vaddr)
-        dataSize = secondAddr - vaddr;
-
-    while(1) {
-        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
-
-        // translate to physical address
-        Fault fault = thread->translateDataReadReq(req);
-
-        //If there's a fault, return it
-        if (fault != NoFault)
-            return fault;
-
-        if (firstTimeThrough) {
-            paddr = req->getPaddr();
-            firstTimeThrough = false;
-        }
-
-        //If we don't need to access a second cache line, stop now.
-        if (secondAddr <= vaddr)
-            return fault;
-
-        /*
-         * Set up for accessing the second cache line.
-         */
-
-        //Adjust the size to get the remaining bytes.
-        dataSize = vaddr + size - secondAddr;
-        //And access the right address.
-        vaddr = secondAddr;
-    }
-}
-
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 template
@@ -507,7 +452,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         req->setVirt(0, addr, dataSize, flags, thread->readPC());
 
         // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
+        Fault fault = thread->dtb->translate(req, tc, true);
 
         // Now do the access.
         if (fault == NoFault) {
@@ -586,64 +531,6 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     }
 }
 
-Fault
-AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    // use the CPU's statically allocated write request and packet objects
-    Request *req = &data_write_req;
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    //The block size of our peer.
-    int blockSize = dcachePort.peerBlockSize();
-
-    //The address of the second part of this access if it needs to be split
-    //across a cache line boundary.
-    Addr secondAddr = roundDown(vaddr + size - 1, blockSize);
-
-    //The size of the data we're trying to read.
-    int dataSize = size;
-
-    bool firstTimeThrough = true;
-
-    if(secondAddr > vaddr)
-        dataSize = secondAddr - vaddr;
-
-    dcache_latency = 0;
-
-    while(1) {
-        req->setVirt(0, vaddr, dataSize, flags, thread->readPC());
-
-        // translate to physical address
-        Fault fault = thread->translateDataWriteReq(req);
-
-        //If there's a fault or we don't need to access a second cache line,
-        //stop now.
-        if (fault != NoFault)
-            return fault;
-
-        if (firstTimeThrough) {
-            paddr = req->getPaddr();
-            firstTimeThrough = false;
-        }
-
-        if (secondAddr <= vaddr)
-            return fault;
-
-        /*
-         * Set up for accessing the second cache line.
-         */
-
-        //Adjust the size to get the remaining bytes.
-        dataSize = vaddr + size - secondAddr;
-        //And access the right address.
-        vaddr = secondAddr;
-    }
-}
-
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 24400df22..190097637 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -136,11 +136,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     template <class T>
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
-    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     /**
      * Print state of address in memory system via PrintReq (for
      * debugging).
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b1a77247f..f9fa8d835 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -347,7 +347,7 @@ BaseSimpleCPU::setupFetchRequest(Request *req)
     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
     req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
 
-    Fault fault = thread->translateInstReq(req);
+    Fault fault = thread->itb->translate(req, tc);
 
     return fault;
 }
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5da08db47..844eccc75 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -275,6 +275,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
     if ((fault = buildPacket(pkt1, req1, read)) != NoFault ||
             (fault = buildPacket(pkt2, req2, read)) != NoFault) {
         delete req;
+        delete req1;
         delete pkt1;
         req = NULL;
         pkt1 = NULL;
@@ -286,6 +287,15 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
     req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
     PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
                                Packet::Broadcast);
+    if (req->getFlags().isSet(Request::NO_ACCESS)) {
+        delete req1;
+        delete pkt1;
+        delete req2;
+        delete pkt2;
+        pkt1 = pkt;
+        pkt2 = NULL;
+        return NoFault;
+    }
 
     pkt->dataDynamic<uint8_t>(data);
     pkt1->dataStatic<uint8_t>(data);
@@ -304,8 +314,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 Fault
 TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr &req, bool read)
 {
-    Fault fault = read ? thread->translateDataReadReq(req) :
-                         thread->translateDataWriteReq(req);
+    Fault fault = thread->dtb->translate(req, tc, !read);
     MemCmd cmd;
     if (fault != NoFault) {
         delete req;
@@ -348,9 +357,13 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
     if (split_addr > addr) {
         PacketPtr pkt1, pkt2;
-        this->buildSplitPacket(pkt1, pkt2, req,
+        Fault fault = this->buildSplitPacket(pkt1, pkt2, req,
                 split_addr, (uint8_t *)(new T), true);
-        if (handleReadPacket(pkt1)) {
+        if (fault != NoFault)
+            return fault;
+        if (req->getFlags().isSet(Request::NO_ACCESS)) {
+            dcache_pkt = pkt1;
+        } else if (handleReadPacket(pkt1)) {
             SplitFragmentSenderState * send_state =
                 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
             send_state->clearFromParent();
@@ -365,9 +378,12 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
         if (fault != NoFault) {
             return fault;
         }
-        pkt->dataDynamic<T>(new T);
-
-        handleReadPacket(pkt);
+        if (req->getFlags().isSet(Request::NO_ACCESS)) {
+            dcache_pkt = pkt;
+        } else {
+            pkt->dataDynamic<T>(new T);
+            handleReadPacket(pkt);
+        }
     }
 
     if (traceData) {
@@ -382,26 +398,6 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
     return NoFault;
 }
 
-Fault
-TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    Fault fault = thread->translateDataWriteReq(req);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 
 template
@@ -497,15 +493,19 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (fault != NoFault)
             return fault;
         dcache_pkt = pkt1;
-        if (handleWritePacket()) {
-            SplitFragmentSenderState * send_state =
-                dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
-            send_state->clearFromParent();
-            dcache_pkt = pkt2;
-            if (handleReadPacket(pkt2)) {
-                send_state =
-                    dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
+        if (!req->getFlags().isSet(Request::NO_ACCESS)) {
+            if (handleWritePacket()) {
+                SplitFragmentSenderState * send_state =
+                    dynamic_cast<SplitFragmentSenderState *>(
+                            pkt1->senderState);
                 send_state->clearFromParent();
+                dcache_pkt = pkt2;
+                if (handleReadPacket(pkt2)) {
+                    send_state =
+                        dynamic_cast<SplitFragmentSenderState *>(
+                                pkt1->senderState);
+                    send_state->clearFromParent();
+                }
             }
         }
     } else {
@@ -515,21 +515,23 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
         if (fault != NoFault)
             return fault;
 
-        if (req->isLocked()) {
-            do_access = TheISA::handleLockedWrite(thread, req);
-        } else if (req->isCondSwap()) {
-            assert(res);
-            req->setExtraData(*res);
-        }
+        if (!req->getFlags().isSet(Request::NO_ACCESS)) {
+            if (req->isLocked()) {
+                do_access = TheISA::handleLockedWrite(thread, req);
+            } else if (req->isCondSwap()) {
+                assert(res);
+                req->setExtraData(*res);
+            }
 
-        dcache_pkt->allocate();
-        if (req->isMmapedIpr())
-            dcache_pkt->set(htog(data));
-        else
-            dcache_pkt->set(data);
+            dcache_pkt->allocate();
+            if (req->isMmapedIpr())
+                dcache_pkt->set(htog(data));
+            else
+                dcache_pkt->set(data);
 
-        if (do_access)
-            handleWritePacket();
+            if (do_access)
+                handleWritePacket();
+        }
     }
 
     if (traceData) {
@@ -546,26 +548,6 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
     return NoFault;
 }
 
-Fault
-TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
-        int size, unsigned flags)
-{
-    Request *req =
-        new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
-
-    if (traceData) {
-        traceData->setAddr(vaddr);
-    }
-
-    Fault fault = thread->translateDataWriteReq(req);
-
-    if (fault == NoFault)
-        paddr = req->getPaddr();
-
-    delete req;
-    return fault;
-}
-
 
 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 template
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index c305d0361..0a639a627 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -224,15 +224,9 @@ class TimingSimpleCPU : public BaseSimpleCPU
     template <class T>
     Fault read(Addr addr, T &data, unsigned flags);
 
-    Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     template <class T>
     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 
-    Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
-            int size, unsigned flags);
-
     void fetch();
     void completeIfetch(PacketPtr );
     void completeDataAccess(PacketPtr );