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authorAndreas Hansson <andreas.hansson@arm.com>2012-04-03 03:50:14 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2012-04-03 03:50:14 -0400
commita8e6adb0b1284e89a63bcb14fe1fdace2b89e0c8 (patch)
tree18965c93c0c5fad292e4a4db8c181240e1a00054 /src/cpu/simple
parenta7859f7e4541f2750df52ec725563d378ab7ddbb (diff)
downloadgem5-a8e6adb0b1284e89a63bcb14fe1fdace2b89e0c8.tar.xz
Atomic: Remove the physmem_port and access memory directly
This patch removes the physmem_port from the Atomic CPU and instead uses the system pointer to access the physmem when using the fastmem option. The system already keeps track of the physmem and the valid memory address ranges, and with this patch we merely make use of that existing functionality. As a result of this change, the overloaded getMasterPort in the Atomic CPU can be removed, thus unifying the CPUs.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/AtomicSimpleCPU.py14
-rw-r--r--src/cpu/simple/atomic.cc43
-rw-r--r--src/cpu/simple/atomic.hh22
3 files changed, 49 insertions, 30 deletions
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 1199f35e1..54daaec63 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -1,3 +1,15 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder. You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
#
@@ -34,4 +46,4 @@ class AtomicSimpleCPU(BaseSimpleCPU):
width = Param.Int(1, "CPU width")
simulate_data_stalls = Param.Bool(False, "Simulate dcache stall cycles")
simulate_inst_stalls = Param.Bool(False, "Simulate icache stall cycles")
- physmem_port = MasterPort("Physical Memory Port")
+ fastmem = Param.Bool(False, "Access memory directly")
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index d7ad07a5e..41bcf9268 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -39,6 +51,7 @@
#include "debug/SimpleCPU.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
+#include "mem/physical.hh"
#include "params/AtomicSimpleCPU.hh"
#include "sim/faults.hh"
#include "sim/system.hh"
@@ -65,17 +78,6 @@ AtomicSimpleCPU::TickEvent::description() const
return "AtomicSimpleCPU tick";
}
-MasterPort &
-AtomicSimpleCPU::getMasterPort(const string &if_name, int idx)
-{
- if (if_name == "physmem_port") {
- hasPhysMemPort = true;
- return physmemPort;
- } else {
- return BaseCPU::getMasterPort(if_name, idx);
- }
-}
-
void
AtomicSimpleCPU::init()
{
@@ -93,8 +95,8 @@ AtomicSimpleCPU::init()
}
}
- if (hasPhysMemPort) {
- AddrRangeList pmAddrList = physmemPort.getSlavePort().getAddrRanges();
+ if (fastmem) {
+ AddrRangeList pmAddrList = system->physmem->getAddrRanges();
physMemAddr = *pmAddrList.begin();
}
// Atomic doesn't do MT right now, so contextId == threadId
@@ -108,7 +110,7 @@ AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams *p)
simulate_data_stalls(p->simulate_data_stalls),
simulate_inst_stalls(p->simulate_inst_stalls),
icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
- physmemPort(name() + "-iport", this), hasPhysMemPort(false)
+ fastmem(p->fastmem)
{
_status = Idle;
}
@@ -281,8 +283,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data,
if (req->isMmappedIpr())
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
else {
- if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
- dcache_latency += physmemPort.sendAtomic(&pkt);
+ if (fastmem && pkt.getAddr() == physMemAddr)
+ dcache_latency += system->physmem->doAtomicAccess(&pkt);
else
dcache_latency += dcachePort.sendAtomic(&pkt);
}
@@ -383,8 +385,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
- if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
- dcache_latency += physmemPort.sendAtomic(&pkt);
+ if (fastmem && pkt.getAddr() == physMemAddr)
+ dcache_latency += system->physmem->doAtomicAccess(&pkt);
else
dcache_latency += dcachePort.sendAtomic(&pkt);
}
@@ -479,8 +481,9 @@ AtomicSimpleCPU::tick()
Packet::Broadcast);
ifetch_pkt.dataStatic(&inst);
- if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
- icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
+ if (fastmem && ifetch_pkt.getAddr() == physMemAddr)
+ icache_latency =
+ system->physmem->doAtomicAccess(&ifetch_pkt);
else
icache_latency = icachePort.sendAtomic(&ifetch_pkt);
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 126cd3765..c0112836a 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -1,4 +1,16 @@
/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved.
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder. You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* All rights reserved.
*
@@ -90,8 +102,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
AtomicCPUPort icachePort;
AtomicCPUPort dcachePort;
- CpuPort physmemPort;
- bool hasPhysMemPort;
+ bool fastmem;
Request ifetch_req;
Request data_read_req;
Request data_write_req;
@@ -111,13 +122,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU
public:
- /**
- * Override the getMasterPort of the BaseCPU so that we can
- * provide the physmemPort, unique to the Atomic CPU.
- */
- virtual MasterPort &getMasterPort(const std::string &if_name,
- int idx = -1);
-
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
virtual void resume();