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authorAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2014-01-24 15:29:30 -0600
commit90b1775a8f87834d4c27d4c98483bb7b1e5e9679 (patch)
tree5c06b3e32bde9938dc977e1a59c288e87075b521 /src/cpu/simple
parent6bed6e0352a68723ea55017b3e09a8c279af11ec (diff)
downloadgem5-90b1775a8f87834d4c27d4c98483bb7b1e5e9679.tar.xz
cpu: Add support for instructions that zero cache lines.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc10
-rw-r--r--src/cpu/simple/timing.cc10
2 files changed, 18 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index b1efbc5ce..f62f891f7 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -399,6 +399,16 @@ Fault
AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
+
+ static uint8_t zero_array[64] = {};
+
+ if (data == NULL) {
+ assert(size <= 64);
+ assert(flags & Request::CACHE_BLOCK_ZERO);
+ // This must be a cache block cleaning request
+ data = zero_array;
+ }
+
// use the CPU's statically allocated write request and packet objects
Request *req = &data_write_req;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 366164e36..3b4f0e7d8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -472,14 +472,20 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
Addr addr, unsigned flags, uint64_t *res)
{
uint8_t *newData = new uint8_t[size];
- memcpy(newData, data, size);
-
const int asid = 0;
const ThreadID tid = 0;
const Addr pc = thread->instAddr();
unsigned block_size = cacheLineSize();
BaseTLB::Mode mode = BaseTLB::Write;
+ if (data == NULL) {
+ assert(flags & Request::CACHE_BLOCK_ZERO);
+ // This must be a cache block cleaning request
+ memset(newData, 0, size);
+ } else {
+ memcpy(newData, data, size);
+ }
+
if (traceData) {
traceData->setAddr(addr);
}