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authorAli Saidi <ali.saidi@arm.com>2014-11-12 09:05:22 -0500
committerAli Saidi <ali.saidi@arm.com>2014-11-12 09:05:22 -0500
commitb6f32253dd504de7873e0087d2d15ba0f227a5b5 (patch)
treea62285b50c8af2aead60077aa5da7497bbab3f57 /src/cpu/simple
parent7d0589512089402cf7bbf585c0e2b4878dc1dd6a (diff)
downloadgem5-b6f32253dd504de7873e0087d2d15ba0f227a5b5.tar.xz
arm: Fix timing wakeup with LLSC
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/timing.cc12
1 files changed, 6 insertions, 6 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 5bfc9799d..2d0ab330e 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -243,6 +243,12 @@ bool
TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
{
RequestPtr req = pkt->req;
+
+ // We're about the issues a locked load, so tell the monitor
+ // to start caring about this address
+ if (pkt->isRead() && pkt->req->isLLSC()) {
+ TheISA::handleLockedRead(thread, pkt->req);
+ }
if (req->isMmappedIpr()) {
Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, clockEdge(delay));
@@ -792,12 +798,6 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
traceData = NULL;
}
- // the locked flag may be cleared on the response packet, so check
- // pkt->req and not pkt to see if it was a load-locked
- if (pkt->isRead() && pkt->req->isLLSC()) {
- TheISA::handleLockedRead(thread, pkt->req);
- }
-
delete pkt->req;
delete pkt;