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authorSteve Reinhardt <stever@eecs.umich.edu>2007-07-02 09:26:36 -0700
committerSteve Reinhardt <stever@eecs.umich.edu>2007-07-02 09:26:36 -0700
commite9c04dad60f7a382fe94ca587fa505926dbd925c (patch)
tree89ccbe4e02cf243d7d2e5560490440a47e2e347a /src/cpu/simple
parentffd697e14933b3012aaaa0fb93168b2fda59ea4a (diff)
downloadgem5-e9c04dad60f7a382fe94ca587fa505926dbd925c.tar.xz
Fix a couple LL/SC bugs that only affected timing mode.
src/cpu/simple/timing.cc: Fix swap/stq_c command bug. src/mem/packet.cc: Fix incorrect LoadLockedReq command response field. --HG-- extra : convert_revision : 7a4523be900bc2c9b1bdf2d372ce55f89ae58ae5
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/timing.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 77df2c05d..492a669b8 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -370,7 +370,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
}
if (do_access) {
- dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
+ dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
dcache_pkt->allocate();
dcache_pkt->set(data);