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author | Dam Sunwoo <dam.sunwoo@arm.com> | 2014-01-24 15:29:30 -0600 |
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committer | Dam Sunwoo <dam.sunwoo@arm.com> | 2014-01-24 15:29:30 -0600 |
commit | 85e8779de78ed913bb6d2a794bee5252d719b0e5 (patch) | |
tree | 8ebd9519b4a6b0590c4d675061a0d1d4b43a1928 /src/cpu/simple | |
parent | 739c6df94ea0030fea04065e6b8d8a1e232752a0 (diff) | |
download | gem5-85e8779de78ed913bb6d2a794bee5252d719b0e5.tar.xz |
mem: per-thread cache occupancy and per-block ages
This patch enables tracking of cache occupancy per thread along with
ages (in buckets) per cache blocks. Cache occupancy stats are
recalculated on each stat dump.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/atomic.cc | 3 | ||||
-rw-r--r-- | src/cpu/simple/timing.cc | 5 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index 13c4b9bd3..617e845a5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -301,6 +301,7 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, dcache_latency = 0; + req->taskId(taskId()); while (1) { req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); @@ -387,6 +388,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, dcache_latency = 0; + req->taskId(taskId()); while(1) { req->setVirt(0, addr, size, flags, dataMasterId(), thread->pcState().instAddr()); @@ -492,6 +494,7 @@ AtomicSimpleCPU::tick() bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst; if (needToFetch) { + ifetch_req.taskId(taskId()); setupFetchRequest(&ifetch_req); fault = thread->itb->translateAtomic(&ifetch_req, tc, BaseTLB::Execute); diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 9253d8005..7996a6ddd 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -415,6 +415,8 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data, RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); + req->taskId(taskId()); + Addr split_addr = roundDown(addr + size - 1, block_size); assert(split_addr <= addr || split_addr - addr < block_size); @@ -484,6 +486,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); + req->taskId(taskId()); + Addr split_addr = roundDown(addr + size - 1, block_size); assert(split_addr <= addr || split_addr - addr < block_size); @@ -561,6 +565,7 @@ TimingSimpleCPU::fetch() if (needToFetch) { _status = BaseSimpleCPU::Running; Request *ifetch_req = new Request(); + ifetch_req->taskId(taskId()); ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); setupFetchRequest(ifetch_req); DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr()); |