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| author | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-02-07 11:35:48 +0000 |
|---|---|---|
| committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | 2017-12-05 11:47:01 +0000 |
| commit | 099cb037e83d1e7bb47ec0e8eaf649a63f889d38 (patch) | |
| tree | da6877f00070e243cb83c233fb5debfdf82a15e2 /src/cpu/simple | |
| parent | 3deff78fe40b9aa3d4e3a8571f13f29072efe4e4 (diff) | |
| download | gem5-099cb037e83d1e7bb47ec0e8eaf649a63f889d38.tar.xz | |
cpu: Add support for CMOs in the cpu models
Cache maintenance operations go through the write channel of the
cpu. This changes makes sure that the cpu does not try to fill in the
packet with data.
Change-Id: Ic83205bb1cda7967636d88f15adcb475eb38d158
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5055
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 7 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 2 |
2 files changed, 3 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index eea7615c8..f3596b6a5 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -430,7 +430,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, if (data == NULL) { assert(size <= 64); - assert(flags & Request::CACHE_BLOCK_ZERO); + assert(flags & Request::STORE_NO_DATA); // This must be a cache block cleaning request data = zero_array; } @@ -462,14 +462,11 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, // Now do the access. if (fault == NoFault) { - MemCmd cmd = MemCmd::WriteReq; // default bool do_access = true; // flag to suppress cache access if (req->isLLSC()) { - cmd = MemCmd::StoreCondReq; do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask); } else if (req->isSwap()) { - cmd = MemCmd::SwapReq; if (req->isCondSwap()) { assert(res); req->setExtraData(*res); @@ -477,7 +474,7 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, Addr addr, } if (do_access && !req->getFlags().isSet(Request::NO_ACCESS)) { - Packet pkt = Packet(req, cmd); + Packet pkt(req, Packet::makeWriteCmd(req)); pkt.dataStatic(data); if (req->isMmappedIpr()) { diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index c38f2107f..961e31935 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -510,7 +510,7 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, BaseTLB::Mode mode = BaseTLB::Write; if (data == NULL) { - assert(flags & Request::CACHE_BLOCK_ZERO); + assert(flags & Request::STORE_NO_DATA); // This must be a cache block cleaning request memset(newData, 0, size); } else { |