arch: Pass faults by const reference where possible

This patch changes how faults are passed between methods in an attempt
to copy as few reference-counting pointer instances as possible. This
should avoid unecessary copies being created, contributing to the
increment/decrement of the reference counters.

4 files changed, 10 insertions, 9 deletions

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index f022d05e0..5130e2960 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -555,7 +555,7 @@ BaseSimpleCPU::postExecute()
 }
 
 void
-BaseSimpleCPU::advancePC(Fault fault)
+BaseSimpleCPU::advancePC(const Fault &fault)
 {
     const bool branching(thread->pcState().branching());
 
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 3755a94a9..43d96fbeb 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -168,7 +168,7 @@ class BaseSimpleCPU : public BaseCPU, public ExecContext
     void setupFetchRequest(Request *req);
     void preExecute();
     void postExecute();
-    void advancePC(Fault fault);
+    void advancePC(const Fault &fault);
 
     virtual void deallocateContext(ThreadID thread_num);
     virtual void haltContext(ThreadID thread_num);
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index f572fc268..9c8f8b57a 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -328,7 +328,7 @@ TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
 }
 
 void
-TimingSimpleCPU::translationFault(Fault fault)
+TimingSimpleCPU::translationFault(const Fault &fault)
 {
     // fault may be NoFault in cases where a fault is suppressed,
     // for instance prefetches.
@@ -576,7 +576,8 @@ TimingSimpleCPU::fetch()
 
 
 void
-TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
+TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
+                           ThreadContext *tc)
 {
     if (fault == NoFault) {
         DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
@@ -608,7 +609,7 @@ TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
 
 
 void
-TimingSimpleCPU::advanceInst(Fault fault)
+TimingSimpleCPU::advanceInst(const Fault &fault)
 {
     if (_status == Faulting)
         return;
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 4a5a20429..a7ea57c67 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -123,7 +123,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
         }
 
         void
-        finish(Fault fault, RequestPtr req, ThreadContext *tc,
+        finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
                BaseTLB::Mode mode)
         {
             cpu->sendFetch(fault, req, tc);
@@ -135,7 +135,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
     void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
                        uint8_t *data, bool read);
 
-    void translationFault(Fault fault);
+    void translationFault(const Fault &fault);
 
     void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
     void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
@@ -280,10 +280,10 @@ class TimingSimpleCPU : public BaseSimpleCPU
                    Addr addr, unsigned flags, uint64_t *res);
 
     void fetch();
-    void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
+    void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
     void completeIfetch(PacketPtr );
     void completeDataAccess(PacketPtr pkt);
-    void advanceInst(Fault fault);
+    void advanceInst(const Fault &fault);
 
     /** This function is used by the page table walker to determine if it could
      * translate the a pending request or if the underlying request has been