add ISA_HAS_DELAY_SLOT directive instead of "#if THE_ISA == ALPHA_ISA" throughout CPU models

src/arch/alpha/isa_traits.hh:
src/arch/mips/isa_traits.hh:
src/arch/sparc/isa_traits.hh:
    define 'ISA_HAS_DELAY_SLOT'
src/cpu/base_dyn_inst.hh:
src/cpu/o3/bpred_unit_impl.hh:
src/cpu/o3/commit_impl.hh:
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/decode_impl.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/iew_impl.hh:
src/cpu/o3/inst_queue_impl.hh:
src/cpu/o3/rename_impl.hh:
src/cpu/simple/base.cc:
    use ISA_HAS_DELAY_SLOT instead of THE_ISA == ALPHA_ISA

--HG--
extra : convert_revision : 24c7460d9391e8d443c9fe08e17c331ae8e9c36a

1 files changed, 7 insertions, 7 deletions

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 801c96c88..22a210115 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -358,12 +358,12 @@ Fault
 BaseSimpleCPU::setupFetchRequest(Request *req)
 {
     // set up memory request for instruction fetch
-#if THE_ISA == ALPHA_ISA
-    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
-            thread->readNextPC());
-#else
+#if ISA_HAS_DELAY_SLOT
     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
             thread->readNextPC(),thread->readNextNPC());
+#else
+    DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
+            thread->readNextPC());
 #endif
 
     req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
@@ -450,12 +450,12 @@ BaseSimpleCPU::advancePC(Fault fault)
     else {
         // go to the next instruction
         thread->setPC(thread->readNextPC());
-#if THE_ISA == ALPHA_ISA
-        thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
-#else
+#if ISA_HAS_DELAY_SLOT
         thread->setNextPC(thread->readNextNPC());
         thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
         assert(thread->readNextPC() != thread->readNextNPC());
+#else
+        thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 #endif
 
     }