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author | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-17 18:50:19 -0400 |
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committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-10-17 18:50:19 -0400 |
commit | 9c582c7e144aef0bfc9d14bb4690d56d1688496a (patch) | |
tree | 986d9a97c38e6ac59f5965b85fe15cd800e6be9a /src/cpu/simple | |
parent | 4fff6d460311d77e0056a546df41366d5a3b4604 (diff) | |
download | gem5-9c582c7e144aef0bfc9d14bb4690d56d1688496a.tar.xz |
Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
--HG--
extra : convert_revision : c4533de421c371c5532ee505e3ecd451511f5c99
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/atomic.cc | 2 | ||||
-rw-r--r-- | src/cpu/simple/timing.cc | 52 |
2 files changed, 33 insertions, 21 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index fe421ae6c..acda254c3 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -101,7 +101,7 @@ AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt) Tick AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt) { - panic("AtomicSimpleCPU doesn't expect recvAtomic callback!"); + //Snooping a coherence request, just return return curTick; } diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index ad5c0e5d6..0cc10ae94 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -528,17 +528,23 @@ TimingSimpleCPU::IcachePort::ITickEvent::process() bool TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) { - // delay processing of returned data until next CPU clock edge - Tick time = pkt->req->getTime(); - while (time < curTick) - time += lat; - - if (time == curTick) - cpu->completeIfetch(pkt); - else - tickEvent.schedule(pkt, time); - - return true; + if (pkt->isResponse()) { + // delay processing of returned data until next CPU clock edge + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; + + if (time == curTick) + cpu->completeIfetch(pkt); + else + tickEvent.schedule(pkt, time); + + return true; + } + else { + //Snooping a Coherence Request, do nothing + return true; + } } void @@ -600,17 +606,23 @@ TimingSimpleCPU::completeDrain() bool TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) { - // delay processing of returned data until next CPU clock edge - Tick time = pkt->req->getTime(); - while (time < curTick) - time += lat; + if (pkt->isResponse()) { + // delay processing of returned data until next CPU clock edge + Tick time = pkt->req->getTime(); + while (time < curTick) + time += lat; - if (time == curTick) - cpu->completeDataAccess(pkt); - else - tickEvent.schedule(pkt, time); + if (time == curTick) + cpu->completeDataAccess(pkt); + else + tickEvent.schedule(pkt, time); - return true; + return true; + } + else { + //Snooping a coherence req, do nothing + return true; + } } void |