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authorMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:40 -0500
committerMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:40 -0500
commit5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7 (patch)
tree3984b0d3f3328901bf8c999b9d01162943fb328d /src/cpu/simple
parent7acf67971cca761efec79a0a0ac453b1115387a9 (diff)
downloadgem5-5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7.tar.xz
ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/base.hh3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 1265a1f2f..90cb81c0c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -287,12 +287,15 @@ class BaseSimpleCPU : public BaseCPU
uint64_t readNextPC() { return thread->readNextPC(); }
uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
uint64_t readNextNPC() { return thread->readNextNPC(); }
+ bool readPredicate() { return thread->readPredicate(); }
void setPC(uint64_t val) { thread->setPC(val); }
void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
void setNextPC(uint64_t val) { thread->setNextPC(val); }
void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
+ void setPredicate(bool val)
+ { return thread->setPredicate(val); }
MiscReg readMiscRegNoEffect(int misc_reg)
{