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authorJoel Hestness <hestness@cs.utexas.edu>2011-02-06 22:14:17 -0800
committerJoel Hestness <hestness@cs.utexas.edu>2011-02-06 22:14:17 -0800
commitb4c10bd6800b5ab5adee3035f1908d7a49a14ca9 (patch)
treed21b1bbf5c8df8c77d77b6983779b24189a1d8cb /src/cpu/simple
parenta679e732cee821616c20cc13c22ad2877072ff14 (diff)
downloadgem5-b4c10bd6800b5ab5adee3035f1908d7a49a14ca9.tar.xz
mcpat: Adds McPAT performance counters
Updated patches from Rick Strong's set that modify performance counters for McPAT
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc1
-rw-r--r--src/cpu/simple/base.cc110
-rw-r--r--src/cpu/simple/base.hh46
-rw-r--r--src/cpu/simple/timing.cc1
4 files changed, 155 insertions, 3 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 35ad46158..da4258fb9 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -212,6 +212,7 @@ AtomicSimpleCPU::resume()
if (!tickEvent.scheduled())
schedule(tickEvent, nextCycle());
}
+ system->totalNumInsts = 0;
}
void
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 13ef0648c..8d7a1b119 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -142,9 +142,69 @@ BaseSimpleCPU::regStats()
.desc("Number of instructions executed")
;
+ numIntAluAccesses
+ .name(name() + ".num_int_alu_accesses")
+ .desc("Number of integer alu accesses")
+ ;
+
+ numFpAluAccesses
+ .name(name() + ".num_fp_alu_accesses")
+ .desc("Number of float alu accesses")
+ ;
+
+ numCallsReturns
+ .name(name() + ".num_func_calls")
+ .desc("number of times a function call or return occured")
+ ;
+
+ numCondCtrlInsts
+ .name(name() + ".num_conditional_control_insts")
+ .desc("number of instructions that are conditional controls")
+ ;
+
+ numIntInsts
+ .name(name() + ".num_int_insts")
+ .desc("number of integer instructions")
+ ;
+
+ numFpInsts
+ .name(name() + ".num_fp_insts")
+ .desc("number of float instructions")
+ ;
+
+ numIntRegReads
+ .name(name() + ".num_int_register_reads")
+ .desc("number of times the integer registers were read")
+ ;
+
+ numIntRegWrites
+ .name(name() + ".num_int_register_writes")
+ .desc("number of times the integer registers were written")
+ ;
+
+ numFpRegReads
+ .name(name() + ".num_fp_register_reads")
+ .desc("number of times the floating registers were read")
+ ;
+
+ numFpRegWrites
+ .name(name() + ".num_fp_register_writes")
+ .desc("number of times the floating registers were written")
+ ;
+
numMemRefs
- .name(name() + ".num_refs")
- .desc("Number of memory references")
+ .name(name()+".num_mem_refs")
+ .desc("number of memory refs")
+ ;
+
+ numStoreInsts
+ .name(name() + ".num_store_insts")
+ .desc("Number of store instructions")
+ ;
+
+ numLoadInsts
+ .name(name() + ".num_load_insts")
+ .desc("Number of load instructions")
;
notIdleFraction
@@ -157,6 +217,16 @@ BaseSimpleCPU::regStats()
.desc("Percentage of idle cycles")
;
+ numBusyCycles
+ .name(name() + ".num_busy_cycles")
+ .desc("Number of busy cycles")
+ ;
+
+ numIdleCycles
+ .name(name()+".num_idle_cycles")
+ .desc("Number of idle cycles")
+ ;
+
icacheStallCycles
.name(name() + ".icache_stall_cycles")
.desc("ICache total stall cycles")
@@ -182,6 +252,8 @@ BaseSimpleCPU::regStats()
;
idleFraction = constant(1.0) - notIdleFraction;
+ numIdleCycles = idleFraction * numCycles;
+ numBusyCycles = (notIdleFraction)*numCycles;
}
void
@@ -277,6 +349,7 @@ BaseSimpleCPU::preExecute()
// check for instruction-count-based events
comInstEventQueue[0]->serviceEvents(numInst);
+ system->instEventQueue.serviceEvents(system->totalNumInsts);
// decode the instruction
inst = gtoh(inst);
@@ -369,6 +442,39 @@ BaseSimpleCPU::postExecute()
CPA::cpa()->swAutoBegin(tc, pc.nextInstAddr());
}
+ /* Power model statistics */
+ //integer alu accesses
+ if (curStaticInst->isInteger()){
+ numIntAluAccesses++;
+ numIntInsts++;
+ }
+
+ //float alu accesses
+ if (curStaticInst->isFloating()){
+ numFpAluAccesses++;
+ numFpInsts++;
+ }
+
+ //number of function calls/returns to get window accesses
+ if (curStaticInst->isCall() || curStaticInst->isReturn()){
+ numCallsReturns++;
+ }
+
+ //the number of branch predictions that will be made
+ if (curStaticInst->isCondCtrl()){
+ numCondCtrlInsts++;
+ }
+
+ //result bus acceses
+ if (curStaticInst->isLoad()){
+ numLoadInsts++;
+ }
+
+ if (curStaticInst->isStore()){
+ numStoreInsts++;
+ }
+ /* End power model statistics */
+
traceFunctions(instAddr);
if (traceData) {
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index bd967b185..628432d76 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -182,7 +182,7 @@ class BaseSimpleCPU : public BaseCPU
{
numInst++;
numInsts++;
-
+ system->totalNumInsts++;
thread->funcExeInst++;
}
@@ -191,8 +191,42 @@ class BaseSimpleCPU : public BaseCPU
return numInst - startNumInst;
}
+ //number of integer alu accesses
+ Stats::Scalar numIntAluAccesses;
+
+ //number of float alu accesses
+ Stats::Scalar numFpAluAccesses;
+
+ //number of function calls/returns
+ Stats::Scalar numCallsReturns;
+
+ //conditional control instructions;
+ Stats::Scalar numCondCtrlInsts;
+
+ //number of int instructions
+ Stats::Scalar numIntInsts;
+
+ //number of float instructions
+ Stats::Scalar numFpInsts;
+
+ //number of integer register file accesses
+ Stats::Scalar numIntRegReads;
+ Stats::Scalar numIntRegWrites;
+
+ //number of float register file accesses
+ Stats::Scalar numFpRegReads;
+ Stats::Scalar numFpRegWrites;
+
// number of simulated memory references
Stats::Scalar numMemRefs;
+ Stats::Scalar numLoadInsts;
+ Stats::Scalar numStoreInsts;
+
+ // number of idle cycles
+ Stats::Formula numIdleCycles;
+
+ // number of busy cycles
+ Stats::Formula numBusyCycles;
// number of simulated loads
Counter numLoad;
@@ -240,28 +274,33 @@ class BaseSimpleCPU : public BaseCPU
uint64_t readIntRegOperand(const StaticInst *si, int idx)
{
+ numIntRegReads++;
return thread->readIntReg(si->srcRegIdx(idx));
}
FloatReg readFloatRegOperand(const StaticInst *si, int idx)
{
+ numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatReg(reg_idx);
}
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
+ numFpRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
return thread->readFloatRegBits(reg_idx);
}
void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
{
+ numIntRegWrites++;
thread->setIntReg(si->destRegIdx(idx), val);
}
void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
{
+ numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatReg(reg_idx, val);
}
@@ -269,6 +308,7 @@ class BaseSimpleCPU : public BaseCPU
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
+ numFpRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
thread->setFloatRegBits(reg_idx, val);
}
@@ -294,16 +334,19 @@ class BaseSimpleCPU : public BaseCPU
MiscReg readMiscReg(int misc_reg)
{
+ numIntRegReads++;
return thread->readMiscReg(misc_reg);
}
void setMiscReg(int misc_reg, const MiscReg &val)
{
+ numIntRegWrites++;
return thread->setMiscReg(misc_reg, val);
}
MiscReg readMiscRegOperand(const StaticInst *si, int idx)
{
+ numIntRegReads++;
int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->readMiscReg(reg_idx);
}
@@ -311,6 +354,7 @@ class BaseSimpleCPU : public BaseCPU
void setMiscRegOperand(
const StaticInst *si, int idx, const MiscReg &val)
{
+ numIntRegWrites++;
int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
return thread->setMiscReg(reg_idx, val);
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 9192c0808..47f99cd6d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -130,6 +130,7 @@ TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
drainEvent = NULL;
previousTick = 0;
changeState(SimObject::Running);
+ system->totalNumInsts = 0;
}