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authorAli Saidi <saidi@eecs.umich.edu>2008-07-01 10:24:16 -0400
committerAli Saidi <saidi@eecs.umich.edu>2008-07-01 10:24:16 -0400
commit50e3e50e1ac592b357a47eecdc3c99a528172870 (patch)
tree1ee6c72dc10691ac920e793646e38c73049f3a8f /src/cpu/simple
parent9bd0bfe559d8c9633c5686ccf100ab921eb6eda2 (diff)
downloadgem5-50e3e50e1ac592b357a47eecdc3c99a528172870.tar.xz
Make the cached virtPort have a thread context so it can do everything that a newly created one can.
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc2
-rw-r--r--src/cpu/simple/timing.cc2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 6b07502ef..0e04a36b2 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -148,7 +148,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
- cpu->tcBase()->connectMemPorts();
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
#endif
}
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2cf7d584d..b86d4b2d7 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -766,7 +766,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
#if FULL_SYSTEM
// Update the ThreadContext's memory ports (Functional/Virtual
// Ports)
- cpu->tcBase()->connectMemPorts();
+ cpu->tcBase()->connectMemPorts(cpu->tcBase());
#endif
}