Automated merge with file:/home/stever/hg/m5-orig

--HG--
extra : convert_revision : 86a55cd98a9704f756a70aa0cbd2820cf92c821d

4 files changed, 17 insertions, 11 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index aa548b46f..2254d44d5 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -55,7 +55,7 @@ AtomicSimpleCPU::TickEvent::process()
 }
 
 const char *
-AtomicSimpleCPU::TickEvent::description()
+AtomicSimpleCPU::TickEvent::description() const
 {
     return "AtomicSimpleCPU tick";
 }
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index f14dd6f99..19bc0e13b 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -68,7 +68,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU
 
         TickEvent(AtomicSimpleCPU *c);
         void process();
-        const char *description();
+        const char *description() const;
     };
 
     TickEvent tickEvent;
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index fc35f2666..9fe3d2fff 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -598,13 +598,19 @@ TimingSimpleCPU::completeIfetch(PacketPtr pkt)
             assert(fault == NoFault);
         } else {
             if (fault == NoFault) {
+                // Note that ARM can have NULL packets if the instruction gets
+                // squashed due to predication
                 // early fail on store conditional: complete now
-                assert(dcache_pkt != NULL);
+                assert(dcache_pkt != NULL || THE_ISA == ARM_ISA);
+
                 fault = curStaticInst->completeAcc(dcache_pkt, this,
                                                    traceData);
-                delete dcache_pkt->req;
-                delete dcache_pkt;
-                dcache_pkt = NULL;
+                if (dcache_pkt != NULL)
+                {
+                    delete dcache_pkt->req;
+                    delete dcache_pkt;
+                    dcache_pkt = NULL;
+                }
 
                 // keep an instruction count
                 if (fault == NoFault)
@@ -816,7 +822,7 @@ TimingSimpleCPU::IprEvent::process()
 }
 
 const char *
-TimingSimpleCPU::IprEvent::description()
+TimingSimpleCPU::IprEvent::description() const
 {
     return "Timing Simple CPU Delay IPR event";
 }
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh
index 79fbe0f5f..f8b77604a 100644
--- a/src/cpu/simple/timing.hh
+++ b/src/cpu/simple/timing.hh
@@ -101,7 +101,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
 
             TickEvent(TimingSimpleCPU *_cpu)
                 :Event(&mainEventQueue), cpu(_cpu) {}
-            const char *description() { return "Timing CPU tick"; }
+            const char *description() const { return "Timing CPU tick"; }
             void schedule(PacketPtr _pkt, Tick t);
         };
 
@@ -127,7 +127,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
             ITickEvent(TimingSimpleCPU *_cpu)
                 : TickEvent(_cpu) {}
             void process();
-            const char *description() { return "Timing CPU icache tick"; }
+            const char *description() const { return "Timing CPU icache tick"; }
         };
 
         ITickEvent tickEvent;
@@ -155,7 +155,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
             DTickEvent(TimingSimpleCPU *_cpu)
                 : TickEvent(_cpu) {}
             void process();
-            const char *description() { return "Timing CPU dcache tick"; }
+            const char *description() const { return "Timing CPU dcache tick"; }
         };
 
         DTickEvent tickEvent;
@@ -219,7 +219,7 @@ class TimingSimpleCPU : public BaseSimpleCPU
         TimingSimpleCPU *cpu;
         IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
         virtual void process();
-        virtual const char *description();
+        virtual const char *description() const;
     };
 
     void completeDrain();