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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:44 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2015-01-25 07:22:44 -0500 |
| commit | 9d8ddd92dc99671db0706413b4f7a7d391d5f58c (patch) | |
| tree | 6d06c4b9acb61fde848cf3c9fba75be643b39b81 /src/cpu/simple | |
| parent | f6742ea26e1a1cac21b486c7c5adad6fb6304e92 (diff) | |
| download | gem5-9d8ddd92dc99671db0706413b4f7a7d391d5f58c.tar.xz | |
sim: Clean up InstRecord
Track memory size and flags as well as add some comments and consts.
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.cc | 10 | ||||
| -rw-r--r-- | src/cpu/simple/timing.cc | 10 |
2 files changed, 8 insertions, 12 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index d1298e3cc..b564521ba 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -317,9 +317,8 @@ AtomicSimpleCPU::readMem(Addr addr, uint8_t * data, // use the CPU's statically allocated read request and packet objects Request *req = &data_read_req; - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); //The size of the data we're trying to read. int fullSize = size; @@ -413,9 +412,8 @@ AtomicSimpleCPU::writeMem(uint8_t *data, unsigned size, // use the CPU's statically allocated write request and packet objects Request *req = &data_write_req; - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); //The size of the data we're trying to read. int fullSize = size; diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index 8c90d7c4e..6de6899e7 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -402,9 +402,8 @@ TimingSimpleCPU::readMem(Addr addr, uint8_t *data, unsigned block_size = cacheLineSize(); BaseTLB::Mode mode = BaseTLB::Read; - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); @@ -479,9 +478,8 @@ TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, memcpy(newData, data, size); } - if (traceData) { - traceData->setAddr(addr); - } + if (traceData) + traceData->setMem(addr, size, flags); RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc, _cpuId, tid); |