diff options
author | Nathan Binkert <nate@binkert.org> | 2009-03-05 19:09:53 -0800 |
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committer | Nathan Binkert <nate@binkert.org> | 2009-03-05 19:09:53 -0800 |
commit | cc95b5739097e31fdaa36a3ff443861969e338b1 (patch) | |
tree | ebcf51fd9ba4480bfb5a444320f8447d1f1ecd2d /src/cpu/simple | |
parent | c7e82f965fa40b4a377a6ddedcdeb542a43ae7c5 (diff) | |
download | gem5-cc95b5739097e31fdaa36a3ff443861969e338b1.tar.xz |
stats: Fix all stats usages to deal with template fixes
Diffstat (limited to 'src/cpu/simple')
-rw-r--r-- | src/cpu/simple/base.hh | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh index d2ccc0ff1..e80606388 100644 --- a/src/cpu/simple/base.hh +++ b/src/cpu/simple/base.hh @@ -177,7 +177,7 @@ class BaseSimpleCPU : public BaseCPU // number of simulated instructions Counter numInst; Counter startNumInst; - Stats::Scalar<> numInsts; + Stats::Scalar numInsts; void countInst() { @@ -196,30 +196,30 @@ class BaseSimpleCPU : public BaseCPU static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1); // number of simulated memory references - Stats::Scalar<> numMemRefs; + Stats::Scalar numMemRefs; // number of simulated loads Counter numLoad; Counter startNumLoad; // number of idle cycles - Stats::Average<> notIdleFraction; + Stats::Average notIdleFraction; Stats::Formula idleFraction; // number of cycles stalled for I-cache responses - Stats::Scalar<> icacheStallCycles; + Stats::Scalar icacheStallCycles; Counter lastIcacheStall; // number of cycles stalled for I-cache retries - Stats::Scalar<> icacheRetryCycles; + Stats::Scalar icacheRetryCycles; Counter lastIcacheRetry; // number of cycles stalled for D-cache responses - Stats::Scalar<> dcacheStallCycles; + Stats::Scalar dcacheStallCycles; Counter lastDcacheStall; // number of cycles stalled for D-cache retries - Stats::Scalar<> dcacheRetryCycles; + Stats::Scalar dcacheRetryCycles; Counter lastDcacheRetry; virtual void serialize(std::ostream &os); |