Merge vm1.(none):/home/stever/bk/newmem-head

into  vm1.(none):/home/stever/bk/newmem-cache2

--HG--
extra : convert_revision : 9002940097a166c8442ae1adf41b974227968920

3 files changed, 10 insertions, 12 deletions

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index ea1c7d87f..03ff1282b 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -521,15 +521,15 @@ AtomicSimpleCPU::tick()
             dcache_access = false; // assume no dcache access
 
             //Fetch more instruction memory if necessary
-            if(predecoder.needMoreBytes())
-            {
+            //if(predecoder.needMoreBytes())
+            //{
                 icache_access = true;
                 ifetch_pkt->reinitFromRequest();
 
                 icache_latency = icachePort.sendAtomic(ifetch_pkt);
                 // ifetch_req is initialized to read the instruction directly
                 // into the CPU object's inst field.
-            }
+            //}
 
             preExecute();
 
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index b7f60522f..9285aa7b5 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -379,11 +379,11 @@ BaseSimpleCPU::preExecute()
         //This should go away once the constructor can be set up properly
         predecoder.setTC(thread->getTC());
         //If more fetch data is needed, pass it in.
-        if(predecoder.needMoreBytes())
-            predecoder.moreBytes(thread->readPC(),
-                    (thread->readPC() & PCMask) + fetchOffset, 0, inst);
-        else
-            predecoder.process();
+        Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
+        //if(predecoder.needMoreBytes())
+            predecoder.moreBytes(thread->readPC(), fetchPC, inst);
+        //else
+        //    predecoder.process();
 
         //If an instruction is ready, decode it. Otherwise, we'll have to
         //fetch beyond the MachInst at the current pc.
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 1c79fcf6b..7698a588d 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -560,8 +560,7 @@ TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick mem_time = pkt->req->getTime();
-        Tick next_tick = cpu->nextCycle(mem_time);
+        Tick next_tick = cpu->nextCycle(curTick);
 
         if (next_tick == curTick)
             cpu->completeIfetch(pkt);
@@ -655,8 +654,7 @@ TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 {
     if (pkt->isResponse()) {
         // delay processing of returned data until next CPU clock edge
-        Tick mem_time = pkt->req->getTime();
-        Tick next_tick = cpu->nextCycle(mem_time);
+        Tick next_tick = cpu->nextCycle(curTick);
 
         if (next_tick == curTick)
             cpu->completeDataAccess(pkt);