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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:31 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-07-09 12:35:31 -0400 |
| commit | 17f9270dada824ab7a1b52ed4470abef5aa56d6c (patch) | |
| tree | f363339d3329d2c01a6e76f653a918a47a47bc2d /src/cpu/simple | |
| parent | ff5718f042ecccee694ae79c9386a589fd77e8ef (diff) | |
| download | gem5-17f9270dada824ab7a1b52ed4470abef5aa56d6c.tar.xz | |
Port: Move retry from port base class to Master/SlavePort
This patch is the last part of moving all protocol-related
functionality out of the Port base class. All the send/recv functions
are already moved, and the retry (which still governs all the timing
transport functions) is the only part that remained in the base class.
The only point where this currently causes a bit of inconvenience is
in the bus where the retry list is global and holds Port pointers (not
Master/SlavePort). This is about to change with the split into a
request/response bus and will soon be removed anyway.
The patch has no impact on any regressions.
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/timing.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index 77057ad02..95edea0b6 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -170,7 +170,7 @@ class TimingSimpleCPU : public BaseSimpleCPU void schedule(PacketPtr _pkt, Tick t); }; - EventWrapper<Port, &Port::sendRetry> retryEvent; + EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent; }; class IcachePort : public TimingCPUPort |