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authorGabe Black <gblack@eecs.umich.edu>2011-03-01 23:18:47 -0800
committerGabe Black <gblack@eecs.umich.edu>2011-03-01 23:18:47 -0800
commit579c5f0b65290b46687273fc58bab5f6f2d17e07 (patch)
tree2c35ef0e67cbb76ef2e58ee49f6c2af098a447b3 /src/cpu/simple
parente8b982e247ad0f096467b85b9018e44c7b89d037 (diff)
downloadgem5-579c5f0b65290b46687273fc58bab5f6f2d17e07.tar.xz
Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped. --HG-- rename : src/arch/alpha/mmaped_ipr.hh => src/arch/alpha/mmapped_ipr.hh rename : src/arch/arm/mmaped_ipr.hh => src/arch/arm/mmapped_ipr.hh rename : src/arch/mips/mmaped_ipr.hh => src/arch/mips/mmapped_ipr.hh rename : src/arch/power/mmaped_ipr.hh => src/arch/power/mmapped_ipr.hh rename : src/arch/sparc/mmaped_ipr.hh => src/arch/sparc/mmapped_ipr.hh rename : src/arch/x86/mmaped_ipr.hh => src/arch/x86/mmapped_ipr.hh
Diffstat (limited to 'src/cpu/simple')
-rw-r--r--src/cpu/simple/atomic.cc6
-rw-r--r--src/cpu/simple/timing.cc8
2 files changed, 7 insertions, 7 deletions
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index da4258fb9..27635d3ce 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -29,7 +29,7 @@
*/
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
@@ -334,7 +334,7 @@ AtomicSimpleCPU::readBytes(Addr addr, uint8_t * data,
Packet::Broadcast);
pkt.dataStatic(data);
- if (req->isMmapedIpr())
+ if (req->isMmappedIpr())
dcache_latency += TheISA::handleIprRead(thread->getTC(), &pkt);
else {
if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
@@ -501,7 +501,7 @@ AtomicSimpleCPU::writeBytes(uint8_t *data, unsigned size,
Packet pkt = Packet(req, cmd, Packet::Broadcast);
pkt.dataStatic(data);
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
dcache_latency +=
TheISA::handleIprWrite(thread->getTC(), &pkt);
} else {
diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index ab1ff91e8..632e83356 100644
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -41,7 +41,7 @@
*/
#include "arch/locked_mem.hh"
-#include "arch/mmaped_ipr.hh"
+#include "arch/mmapped_ipr.hh"
#include "arch/utility.hh"
#include "base/bigint.hh"
#include "config/the_isa.hh"
@@ -264,7 +264,7 @@ bool
TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
{
RequestPtr req = pkt->req;
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
Tick delay;
delay = TheISA::handleIprRead(thread->getTC(), pkt);
new IprEvent(pkt, this, nextCycle(curTick() + delay));
@@ -401,7 +401,7 @@ TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
{
pkt1 = pkt2 = NULL;
- assert(!req1->isMmapedIpr() && !req2->isMmapedIpr());
+ assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
if (req->getFlags().isSet(Request::NO_ACCESS)) {
buildPacket(pkt1, req, read);
@@ -536,7 +536,7 @@ bool
TimingSimpleCPU::handleWritePacket()
{
RequestPtr req = dcache_pkt->req;
- if (req->isMmapedIpr()) {
+ if (req->isMmappedIpr()) {
Tick delay;
delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));