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| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:24 -0500 |
| commit | fbdeb6031664d71e19a25f51b6ee882d803dac30 (patch) | |
| tree | 0a3fa9a980e9b9a1013b3aff37080b045192b650 /src/cpu/simple | |
| parent | bead7f249a71f8b15ae92b0df9822abb52ca7323 (diff) | |
| download | gem5-fbdeb6031664d71e19a25f51b6ee882d803dac30.tar.xz | |
mem: Deduce if cache should forward snoops
This patch changes how the cache determines if snoops should be
forwarded from the memory side to the CPU side. Instead of having a
parameter, the cache now looks at the port connected on the CPU side,
and if it is a snooping port, then snoops are forwarded. Less error
prone, and less parameters to worry about.
The patch also tidies up the CPU classes to ensure that their I-side
port is not snooping by removing overrides to the snoop request
handler, such that snoop requests will panic via the default
MasterPort implement
Diffstat (limited to 'src/cpu/simple')
| -rw-r--r-- | src/cpu/simple/atomic.hh | 1 | ||||
| -rw-r--r-- | src/cpu/simple/timing.hh | 5 |
2 files changed, 0 insertions, 6 deletions
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index c643bfe58..098ecd759 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -127,7 +127,6 @@ class AtomicSimpleCPU : public BaseSimpleCPU { } protected: - virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; } bool recvTimingResp(PacketPtr pkt) { diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index da8320793..035f05158 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -164,11 +164,6 @@ class TimingSimpleCPU : public BaseSimpleCPU protected: - /** - * Snooping a coherence request, do nothing. - */ - virtual void recvTimingSnoopReq(PacketPtr pkt) {} - TimingSimpleCPU* cpu; struct TickEvent : public Event |