summaryrefslogtreecommitdiff
path: root/src/cpu/simple_thread.cc
diff options
context:
space:
mode:
authorAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:42 -0500
committerAndreas Sandberg <Andreas.Sandberg@ARM.com>2013-01-07 13:05:42 -0500
commit17b47d35e1d0dedca7a3336f1193b1a502bcd78b (patch)
tree3b37175b174a2cdad1020ff6dd917f32c1c10907 /src/cpu/simple_thread.cc
parent7eb0fb8b6ebffcb39b61964d4c7387455c262aae (diff)
downloadgem5-17b47d35e1d0dedca7a3336f1193b1a502bcd78b.tar.xz
arch: Move the ISA object to a separate section
After making the ISA an independent SimObject, it is serialized automatically by the Python world. Previously, this just resulted in an empty ISA section. This patch moves the contents of the ISA to that section and removes the explicit ISA serialization from the thread contexts, which makes it behave like a normal SimObject during serialization. Note: This patch breaks checkpoint backwards compatibility! Use the cpt_upgrader.py utility to upgrade old checkpoints to the new format.
Diffstat (limited to 'src/cpu/simple_thread.cc')
-rw-r--r--src/cpu/simple_thread.cc10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index af121e43f..d2171a0e4 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -179,11 +179,6 @@ SimpleThread::serialize(ostream &os)
SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
_pcState.serialize(os);
// thread_num and cpu_id are deterministic from the config
-
- //
- // Now must serialize all the ISA dependent state
- //
- isa->serialize(baseCpu, os);
}
@@ -195,11 +190,6 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs);
_pcState.unserialize(cp, section);
// thread_num and cpu_id are deterministic from the config
-
- //
- // Now must unserialize all the ISA dependent state
- //
- isa->unserialize(baseCpu, cp, section);
}
void