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| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-23 14:31:36 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-11-28 14:15:36 +0000 |
| commit | d3ecb5d406a3dc12c53a20c271db3027b8477c39 (patch) | |
| tree | d77795322eaf8a7e2df2e04df649d07d51e8d8cc /src/cpu/simple_thread.cc | |
| parent | 7c1405402c7c53f17e554f584b7e801f1f755034 (diff) | |
| download | gem5-d3ecb5d406a3dc12c53a20c271db3027b8477c39.tar.xz | |
cpu-o3: Add missing vector stat initializers
All of the O3 vector stats added by 'arch: ISA parser additions of
vector registers' are currently missing their stat initializers. Add
the missing stat initialization to InstructionQueue::regStats.
Change-Id: Idc4b8e2824120a2542d8a604340a1b41bde6aa28
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/6101
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Diffstat (limited to 'src/cpu/simple_thread.cc')
0 files changed, 0 insertions, 0 deletions