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author | Kevin Lim <ktlim@umich.edu> | 2006-10-31 14:33:56 -0500 |
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committer | Kevin Lim <ktlim@umich.edu> | 2006-10-31 14:33:56 -0500 |
commit | bfd5eb2b08dad700d085a637d5e16a61dcc530d7 (patch) | |
tree | d8a5404b828f37287a020ca028a4ea8fc13a106b /src/cpu/simple_thread.cc | |
parent | b26355daa87c7a86a96a90b2002bc5684741288c (diff) | |
download | gem5-bfd5eb2b08dad700d085a637d5e16a61dcc530d7.tar.xz |
Remove mem parameter. Now the translating port asks the CPU's dcache's peer for its MemObject instead of having to have a paramter for the MemObject.
configs/example/fs.py:
configs/example/se.py:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
src/cpu/simple_thread.cc:
src/cpu/simple_thread.hh:
src/cpu/thread_state.cc:
src/cpu/thread_state.hh:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-atomic.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
No need for mem parameter any more.
src/cpu/checker/cpu.cc:
Use new constructor for simple thread (no more MemObject parameter).
src/cpu/checker/cpu.hh:
Remove MemObject parameter.
src/cpu/memtest/memtest.hh:
Ports now take in their MemObject owner.
src/cpu/o3/alpha/cpu_builder.cc:
Remove mem parameter.
src/cpu/o3/alpha/cpu_impl.hh:
Remove memory parameter and clean up handling of TranslatingPort.
src/cpu/o3/cpu.cc:
src/cpu/o3/cpu.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/mips/cpu_builder.cc:
src/cpu/o3/mips/cpu_impl.hh:
src/cpu/o3/params.hh:
src/cpu/o3/thread_state.hh:
src/cpu/ozone/cpu.hh:
src/cpu/ozone/cpu_builder.cc:
src/cpu/ozone/cpu_impl.hh:
src/cpu/ozone/front_end.hh:
src/cpu/ozone/front_end_impl.hh:
src/cpu/ozone/lw_lsq.hh:
src/cpu/ozone/lw_lsq_impl.hh:
src/cpu/ozone/simple_params.hh:
src/cpu/ozone/thread_state.hh:
src/cpu/simple/atomic.cc:
Remove memory parameter.
--HG--
extra : convert_revision : 43cb44a33b31320d44b69679dcf646c0380d07d3
Diffstat (limited to 'src/cpu/simple_thread.cc')
-rw-r--r-- | src/cpu/simple_thread.cc | 38 |
1 files changed, 24 insertions, 14 deletions
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 4fc47c982..c89a13eef 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -62,7 +62,7 @@ using namespace std; SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, AlphaITB *_itb, AlphaDTB *_dtb, bool use_kernel_stats) - : ThreadState(-1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), + : ThreadState(_cpu, -1, _thread_num), cpu(_cpu), system(_sys), itb(_itb), dtb(_dtb) { @@ -106,19 +106,10 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, } #else SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, - Process *_process, int _asid, MemObject* memobj) - : ThreadState(-1, _thread_num, _process, _asid, memobj), + Process *_process, int _asid) + : ThreadState(_cpu, -1, _thread_num, _process, _asid), cpu(_cpu) { - /* Use this port to for syscall emulation writes to memory. */ - Port *mem_port; - port = new TranslatingPort(csprintf("%s-%d-funcport", - cpu->name(), tid), - process->pTable, false); - mem_port = memobj->getPort("functional"); - mem_port->setPeer(port); - port->setPeer(mem_port); - regs.clear(); tc = new ProxyThreadContext<SimpleThread>(this); } @@ -127,9 +118,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, SimpleThread::SimpleThread() #if FULL_SYSTEM - : ThreadState(-1, -1) + : ThreadState(NULL, -1, -1) #else - : ThreadState(-1, -1, NULL, -1, NULL) + : ThreadState(NULL, -1, -1, NULL, -1) #endif { tc = new ProxyThreadContext<SimpleThread>(this); @@ -332,6 +323,25 @@ SimpleThread::delVirtPort(VirtualPort *vp) } } +#else +TranslatingPort * +SimpleThread::getMemPort() +{ + if (port != NULL) + return port; + + /* Use this port to for syscall emulation writes to memory. */ + Port *dcache_port; + port = new TranslatingPort(csprintf("%s-%d-funcport", + cpu->name(), tid), + process->pTable, false); + dcache_port = cpu->getPort("dcache_port"); + assert(dcache_port != NULL); + dcache_port = dcache_port->getPeer(); +// mem_port->setPeer(port); + port->setPeer(dcache_port); + return port; +} #endif |