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authorGabe Black <gblack@eecs.umich.edu>2009-07-29 00:15:26 -0700
committerGabe Black <gblack@eecs.umich.edu>2009-07-29 00:15:26 -0700
commit2871a13ab31aaabea93f1d55595e199ea76e9dcf (patch)
treec2a0fe2c73e9b9e3ab35ba35e4b28c09174c2491 /src/cpu/simple_thread.hh
parent873112ea9924074212f1dd667d345850c6dce789 (diff)
downloadgem5-2871a13ab31aaabea93f1d55595e199ea76e9dcf.tar.xz
Simple CPU: Make the simple CPU handle the IntRegs trace flag.
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index d9d624e77..8a44eba37 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -262,7 +262,9 @@ class SimpleThread : public ThreadState
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
- return intRegs[flatIndex];
+ uint64_t regVal = intRegs[flatIndex];
+ DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
+ return regVal;
}
FloatReg readFloatReg(int reg_idx)
@@ -283,6 +285,7 @@ class SimpleThread : public ThreadState
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
+ DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
intRegs[flatIndex] = val;
}