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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:21 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:21 -0700 |
| commit | 5c37d10624e0f9a9568f1eb1527832c55addba59 (patch) | |
| tree | 7283390137489bc23fd4685e6ede83925479ee48 /src/cpu/simple_thread.hh | |
| parent | 9bf22992ee1f5088ae5e513acaa7aabee048c4bd (diff) | |
| download | gem5-5c37d10624e0f9a9568f1eb1527832c55addba59.tar.xz | |
Registers: Eliminate the ISA defined RegFile class.
Diffstat (limited to 'src/cpu/simple_thread.hh')
| -rw-r--r-- | src/cpu/simple_thread.hh | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 31e69bafe..90502fe9f 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -90,7 +90,6 @@ class TranslatingPort; class SimpleThread : public ThreadState { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; @@ -99,7 +98,6 @@ class SimpleThread : public ThreadState typedef ThreadContext::Status Status; protected: - RegFile regs; // correct-path register context union { FloatReg f[TheISA::NumFloatRegs]; FloatRegBits i[TheISA::NumFloatRegs]; @@ -253,7 +251,6 @@ class SimpleThread : public ThreadState void clearArchRegs() { - regs.clear(); microPC = 0; nextMicroPC = 1; PC = nextPC = nextNPC = 0; |