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authorMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:40 -0500
committerMin Kyu Jeong <minkyu.jeong@arm.com>2010-08-23 11:18:40 -0500
commit5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7 (patch)
tree3984b0d3f3328901bf8c999b9d01162943fb328d /src/cpu/simple_thread.hh
parent7acf67971cca761efec79a0a0ac453b1115387a9 (diff)
downloadgem5-5f91ec3f4618dad8d36efbf8b5a5112a1ce0d1b7.tar.xz
ARM/O3: store the result of the predicate evaluation in DynInst or Threadstate.
THis allows the CPU to handle predicated-false instructions accordingly. This particular patch makes loads that are predicated-false to be sent straight to the commit stage directly, not waiting for return of the data that was never requested since it was predicated-false.
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh13
1 files changed, 13 insertions, 0 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index bc8588041..dcd933ffc 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -128,6 +128,9 @@ class SimpleThread : public ThreadState
*/
Addr nextNPC;
+ /** Did this instruction execute or is it predicated false */
+ bool predicate;
+
public:
// pointer to CPU associated with this SimpleThread
BaseCPU *cpu;
@@ -371,6 +374,16 @@ class SimpleThread : public ThreadState
#endif
}
+ bool readPredicate()
+ {
+ return predicate;
+ }
+
+ void setPredicate(bool val)
+ {
+ predicate = val;
+ }
+
MiscReg
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
{