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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-04-29 16:05:02 -0500 |
| commit | 4a3f11149d791284a012af71067f6b2199aa165c (patch) | |
| tree | c960b2f2c5e23fc37e238f423a8bbc3b73419213 /src/cpu/simple_thread.hh | |
| parent | 035a82ee2c7e9ee72163a6559f721b242427906d (diff) | |
| download | gem5-4a3f11149d791284a012af71067f6b2199aa165c.tar.xz | |
arm: use condition code registers for ARM ISA
Analogous to ee049bf (for x86). Requires a bump of the checkpoint version
and corresponding upgrader code to move the condition code register values
to the new register file.
Diffstat (limited to 'src/cpu/simple_thread.hh')
| -rw-r--r-- | src/cpu/simple_thread.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index c5fae4e8e..710a5af78 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -273,6 +273,7 @@ class SimpleThread : public ThreadState { #ifdef ISA_HAS_CC_REGS int flatIndex = isa->flattenCCIndex(reg_idx); + assert(0 <= flatIndex); assert(flatIndex < TheISA::NumCCRegs); uint64_t regVal(readCCRegFlat(flatIndex)); DPRINTF(CCRegs, "Reading CC reg %d (%d) as %#x.\n", |