diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-12 10:58:45 -0400 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-12 10:58:45 -0400 |
| commit | 866cfaf9dc596d8547e14bc2133fb962776572a7 (patch) | |
| tree | 19b82a8021533e8bc2e35f14fb0b6a0440756814 /src/cpu/simple_thread.hh | |
| parent | 6a31898a88a9ecced399ccf50636831c21d4a75e (diff) | |
| parent | 78aec04b660544ea7af80d76912b4422c4426602 (diff) | |
| download | gem5-866cfaf9dc596d8547e14bc2133fb962776572a7.tar.xz | |
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem
--HG--
extra : convert_revision : 30b2475ba034550376455e1bc0e52e19a200fd5a
Diffstat (limited to 'src/cpu/simple_thread.hh')
| -rw-r--r-- | src/cpu/simple_thread.hh | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 242cfd0e1..6fa6500bd 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -237,7 +237,7 @@ class SimpleThread : public ThreadState Fault read(RequestPtr &req, T &data) { #if FULL_SYSTEM && THE_ISA == ALPHA_ISA - if (req->flags & LOCKED) { + if (req->isLocked()) { req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); } @@ -256,10 +256,10 @@ class SimpleThread : public ThreadState ExecContext *xc; // If this is a store conditional, act appropriately - if (req->flags & LOCKED) { + if (req->isLocked()) { xc = req->xc; - if (req->flags & UNCACHEABLE) { + if (req->isUncacheable()) { // Don't update result register (see stq_c in isa_desc) req->result = 2; xc->setStCondFailures(0);//Needed? [RGD] |