cpu: Simplify the rename interface and use RegId

With the hierarchical RegId there are a lot of functions that are
redundant now.

The idea behind the simplification is that instead of having the regId,
telling which kind of register read/write/rename/lookup/etc. and then
the function panic_if'ing if the regId is not of the appropriate type,
we provide an interface that decides what kind of register to read
depending on the register type of the given regId.

Change-Id: I7d52e9e21fc01205ae365d86921a4ceb67a57178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2702

1 files changed, 3 insertions, 21 deletions

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index bdf93b0e4..286d91766 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -401,28 +401,10 @@ class SimpleThread : public ThreadState
         return isa->setMiscReg(misc_reg, val, tc);
     }
 
-    int
-    flattenIntIndex(int reg)
+    RegId
+    flattenRegId(const RegId& regId) const
     {
-        return isa->flattenIntIndex(reg);
-    }
-
-    int
-    flattenFloatIndex(int reg)
-    {
-        return isa->flattenFloatIndex(reg);
-    }
-
-    int
-    flattenCCIndex(int reg)
-    {
-        return isa->flattenCCIndex(reg);
-    }
-
-    int
-    flattenMiscIndex(int reg)
-    {
-        return isa->flattenMiscIndex(reg);
+        return isa->flattenRegId(regId);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }