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author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:44 -0500 |
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committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:44 -0500 |
commit | e2dad8236a95b5d7b1c1470385d0b543d3c7af4a (patch) | |
tree | 5b10bce38b63a506733c0d219a8abecce1eb013d /src/cpu/simple_thread.hh | |
parent | 17b47d35e1d0dedca7a3336f1193b1a502bcd78b (diff) | |
download | gem5-e2dad8236a95b5d7b1c1470385d0b543d3c7af4a.tar.xz |
cpu: Implement a flat register interface in thread contexts
Some architectures map registers differently depending on their mode
of operations. There is currently no architecture independent way of
accessing all registers. This patch introduces a flat register
interface to the ThreadContext class. This interface is useful, for
example, when serializing or copying thread contexts.
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r-- | src/cpu/simple_thread.hh | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 8e6df9466..33dcdd49d 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -237,7 +237,7 @@ class SimpleThread : public ThreadState { int flatIndex = isa->flattenIntIndex(reg_idx); assert(flatIndex < TheISA::NumIntRegs); - uint64_t regVal = intRegs[flatIndex]; + uint64_t regVal(readIntRegFlat(flatIndex)); DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n", reg_idx, flatIndex, regVal); return regVal; @@ -247,7 +247,7 @@ class SimpleThread : public ThreadState { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - FloatReg regVal = floatRegs.f[flatIndex]; + FloatReg regVal(readFloatRegFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n", reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]); return regVal; @@ -257,7 +257,7 @@ class SimpleThread : public ThreadState { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - FloatRegBits regVal = floatRegs.i[flatIndex]; + FloatRegBits regVal(readFloatRegBitsFlat(flatIndex)); DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n", reg_idx, flatIndex, regVal, floatRegs.f[flatIndex]); return regVal; @@ -269,14 +269,14 @@ class SimpleThread : public ThreadState assert(flatIndex < TheISA::NumIntRegs); DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n", reg_idx, flatIndex, val); - intRegs[flatIndex] = val; + setIntRegFlat(flatIndex, val); } void setFloatReg(int reg_idx, FloatReg val) { int flatIndex = isa->flattenFloatIndex(reg_idx); assert(flatIndex < TheISA::NumFloatRegs); - floatRegs.f[flatIndex] = val; + setFloatRegFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n", reg_idx, flatIndex, val, floatRegs.i[flatIndex]); } @@ -288,7 +288,7 @@ class SimpleThread : public ThreadState // XXX: Fix array out of bounds compiler error for gem5.fast // when checkercpu enabled if (flatIndex < TheISA::NumFloatRegs) - floatRegs.i[flatIndex] = val; + setFloatRegBitsFlat(flatIndex, val); DPRINTF(FloatRegs, "Setting float reg %d (%d) bits to %#x, %#f.\n", reg_idx, flatIndex, val, floatRegs.f[flatIndex]); } @@ -384,6 +384,18 @@ class SimpleThread : public ThreadState { process->syscall(callnum, tc); } + + uint64_t readIntRegFlat(int idx) { return intRegs[idx]; } + void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; } + + FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; } + void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; } + + FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; } + void setFloatRegBitsFlat(int idx, FloatRegBits val) { + floatRegs.i[idx] = val; + } + }; |