diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-01-24 15:29:30 -0600 |
| commit | 7d0344704a9ecc566d82ad43ec44b4becbaf4d77 (patch) | |
| tree | 4281e9fe0ff9480698ed697027e411da73e78d47 /src/cpu/simple_thread.hh | |
| parent | 3436de0c2ad467c65066e48969a7c12bdbbb3d26 (diff) | |
| download | gem5-7d0344704a9ecc566d82ad43ec44b4becbaf4d77.tar.xz | |
arch, cpu: Add support for flattening misc register indexes.
With ARMv8 support the same misc register id results in accessing different
registers depending on the current mode of the processor. This patch adds
the same orthogonality to the misc register file as the others (int, float, cc).
For all the othre ISAs this is currently a null-implementation.
Additionally, a system variable is added to all the ISA objects.
Diffstat (limited to 'src/cpu/simple_thread.hh')
| -rw-r--r-- | src/cpu/simple_thread.hh | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index fa0d20b0a..c5fae4e8e 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011 ARM Limited + * Copyright (c) 2011-2012 ARM Limited * Copyright (c) 2013 Advanced Micro Devices, Inc. * All rights reserved * @@ -415,6 +415,12 @@ class SimpleThread : public ThreadState return isa->flattenCCIndex(reg); } + int + flattenMiscIndex(int reg) + { + return isa->flattenMiscIndex(reg); + } + unsigned readStCondFailures() { return storeCondFailures; } void setStCondFailures(unsigned sc_failures) |