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authorKorey Sewell <ksewell@umich.edu>2009-07-31 10:40:42 -0400
committerKorey Sewell <ksewell@umich.edu>2009-07-31 10:40:42 -0400
commitaa75b9a7a7489bf86c4e6d406ff612e596ddff96 (patch)
tree58a6816583a21c19c181e32bff10bf74aa9ad15f /src/cpu/simple_thread.hh
parent60063cc700912666fa8b7968d692d00a1e82cb67 (diff)
parent3dd3de5feb31055a48acb39575da25a9cea2626d (diff)
downloadgem5-aa75b9a7a7489bf86c4e6d406ff612e596ddff96.tar.xz
merge mips fix and statetrace changes
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index d9d624e77..8a44eba37 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -262,7 +262,9 @@ class SimpleThread : public ThreadState
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
- return intRegs[flatIndex];
+ uint64_t regVal = intRegs[flatIndex];
+ DPRINTF(IntRegs, "Reading int reg %d as %#x.\n", reg_idx, regVal);
+ return regVal;
}
FloatReg readFloatReg(int reg_idx)
@@ -283,6 +285,7 @@ class SimpleThread : public ThreadState
{
int flatIndex = isa.flattenIntIndex(reg_idx);
assert(flatIndex < TheISA::NumIntRegs);
+ DPRINTF(IntRegs, "Setting int reg %d to %#x.\n", reg_idx, val);
intRegs[flatIndex] = val;
}