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authorKorey Sewell <ksewell@umich.edu>2007-06-22 19:03:42 -0400
committerKorey Sewell <ksewell@umich.edu>2007-06-22 19:03:42 -0400
commit753adb38d5471d23315d1bcfc6a744d1c6e03975 (patch)
tree9ae1cc842f4c3756acf86147a5fd6772d7a6622f /src/cpu/simple_thread.hh
parent16c1b5484f576b6aebea9ab5ffab4ea64f080de0 (diff)
downloadgem5-753adb38d5471d23315d1bcfc6a744d1c6e03975.tar.xz
mips import pt. 1
src/arch/mips/SConscript: "mips import pt.1". --HG-- extra : convert_revision : 2e393341938bebf32fb638a209262d074fad4cc1
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 95848ee2c..c20fe3d90 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -349,22 +349,22 @@ class SimpleThread : public ThreadState
regs.setNextNPC(val);
}
- MiscReg readMiscRegNoEffect(int misc_reg)
+ MiscReg readMiscRegNoEffect(int misc_reg, unsigned tid = 0)
{
return regs.readMiscRegNoEffect(misc_reg);
}
- MiscReg readMiscReg(int misc_reg)
+ MiscReg readMiscReg(int misc_reg, unsigned tid = 0)
{
return regs.readMiscReg(misc_reg, tc);
}
- void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
+ void setMiscRegNoEffect(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
return regs.setMiscRegNoEffect(misc_reg, val);
}
- void setMiscReg(int misc_reg, const MiscReg &val)
+ void setMiscReg(int misc_reg, const MiscReg &val, unsigned tid = 0)
{
return regs.setMiscReg(misc_reg, val, tc);
}