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authorGabe Black <gblack@eecs.umich.edu>2007-07-26 22:13:14 -0700
committerGabe Black <gblack@eecs.umich.edu>2007-07-26 22:13:14 -0700
commitd1e533a1e243b75b3257e2f96deb385a3b10e09b (patch)
tree5cde70506a663c83efceced11273cca47fed9586 /src/cpu/simple_thread.hh
parent876849724d0e5a990018dc025a8166c5131be567 (diff)
downloadgem5-d1e533a1e243b75b3257e2f96deb385a3b10e09b.tar.xz
X86: Fix argument register indexing.
Code was assuming that all argument registers followed in order from ArgumentReg0. There is now an ArgumentReg array which is indexed to find the right index. There is a constant, NumArgumentRegs, which can be used to protect against using an invalid ArgumentReg. --HG-- extra : convert_revision : f448a3ca4d6adc3fc3323562870f70eec05a8a1f
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r--src/cpu/simple_thread.hh6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index c20fe3d90..6c6d5f842 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -377,15 +377,17 @@ class SimpleThread : public ThreadState
#if !FULL_SYSTEM
TheISA::IntReg getSyscallArg(int i)
{
+ assert(i < TheISA::NumArgumentRegs);
return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg0 + i));
+ TheISA::ArgumentReg[i]));
}
// used to shift args for indirect syscall
void setSyscallArg(int i, TheISA::IntReg val)
{
+ assert(i < TheISA::NumArgumentRegs);
regs.setIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg0 + i), val);
+ TheISA::ArgumentReg[i]), val);
}
void setSyscallReturn(SyscallReturn return_value)