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author | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2007-08-26 20:24:18 -0700 |
commit | 537239b278f7b8171d2eb09ef7f99c332266c48f (patch) | |
tree | 31984b63cc542f0a57ca96262477575ab0130c09 /src/cpu/simple_thread.hh | |
parent | f738afb865cd82487d6300259d6e87fb50660d2a (diff) | |
download | gem5-537239b278f7b8171d2eb09ef7f99c332266c48f.tar.xz |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
--HG--
extra : convert_revision : a04a30df0b6246e877a1cea35420dbac94b506b1
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r-- | src/cpu/simple_thread.hh | 36 |
1 files changed, 10 insertions, 26 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 6c6d5f842..1e87b0bb7 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -35,6 +35,7 @@ #include "arch/isa_traits.hh" #include "arch/regfile.hh" #include "arch/syscallreturn.hh" +#include "arch/tlb.hh" #include "config/full_system.hh" #include "cpu/thread_context.hh" #include "cpu/thread_state.hh" @@ -49,7 +50,6 @@ class BaseCPU; #if FULL_SYSTEM #include "sim/system.hh" -#include "arch/tlb.hh" class FunctionProfile; class ProfileNode; @@ -109,10 +109,8 @@ class SimpleThread : public ThreadState System *system; -#if FULL_SYSTEM TheISA::ITB *itb; TheISA::DTB *dtb; -#endif // constructor: initialize SimpleThread from given process structure #if FULL_SYSTEM @@ -120,7 +118,8 @@ class SimpleThread : public ThreadState TheISA::ITB *_itb, TheISA::DTB *_dtb, bool use_kernel_stats = true); #else - SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid); + SimpleThread(BaseCPU *_cpu, int _thread_num, Process *_process, + TheISA::ITB *_itb, TheISA::DTB *_dtb, int _asid); #endif SimpleThread(); @@ -149,10 +148,6 @@ class SimpleThread : public ThreadState */ ThreadContext *getTC() { return tc; } -#if FULL_SYSTEM - int getInstAsid() { return regs.instAsid(); } - int getDataAsid() { return regs.dataAsid(); } - Fault translateInstReq(RequestPtr &req) { return itb->translate(req, tc); @@ -168,27 +163,16 @@ class SimpleThread : public ThreadState return dtb->translate(req, tc, true); } +#if FULL_SYSTEM + int getInstAsid() { return regs.instAsid(); } + int getDataAsid() { return regs.dataAsid(); } + void dumpFuncProfile(); Fault hwrei(); bool simPalCheck(int palFunc); -#else - - Fault translateInstReq(RequestPtr &req) - { - return process->pTable->translate(req); - } - - Fault translateDataReadReq(RequestPtr &req) - { - return process->pTable->translate(req); - } - Fault translateDataWriteReq(RequestPtr &req) - { - return process->pTable->translate(req); - } #endif /******************************************* @@ -199,13 +183,13 @@ class SimpleThread : public ThreadState int getThreadNum() { return tid; } -#if FULL_SYSTEM - System *getSystemPtr() { return system; } - TheISA::ITB *getITBPtr() { return itb; } TheISA::DTB *getDTBPtr() { return dtb; } +#if FULL_SYSTEM + System *getSystemPtr() { return system; } + FunctionalPort *getPhysPort() { return physPort; } /** Return a virtual port. If no thread context is specified then a static |