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author | Gabe Black <gblack@eecs.umich.edu> | 2006-12-12 18:10:00 -0500 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2006-12-12 18:10:00 -0500 |
commit | 90907f6b3cc79ec3e4bac2af7ef506672bab91e1 (patch) | |
tree | c089d7170e29e6829e420268ece72c0eeab0e820 /src/cpu/simple_thread.hh | |
parent | 498e235ae0612d268001f813de6031fcdfc76de7 (diff) | |
parent | 6c8c86f2f97913788237f763d4810ab12730ca60 (diff) | |
download | gem5-90907f6b3cc79ec3e4bac2af7ef506672bab91e1.tar.xz |
Merge zizzer:/bk/newmem/
into zower.eecs.umich.edu:/eecshome/m5/newmem
--HG--
extra : convert_revision : 17d6c49ee15af5d192dedf82871159219d4277cd
Diffstat (limited to 'src/cpu/simple_thread.hh')
-rw-r--r-- | src/cpu/simple_thread.hh | 69 |
1 files changed, 0 insertions, 69 deletions
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index acbefeb67..f2f79c070 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -234,75 +234,6 @@ class SimpleThread : public ThreadState /// Set the status to Halted. void halt(); -/* - template <class T> - Fault read(RequestPtr &req, T &data) - { -#if FULL_SYSTEM && THE_ISA == ALPHA_ISA - if (req->isLocked()) { - req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr); - req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true); - } -#endif - - Fault error; - error = mem->prot_read(req->paddr, data, req->size); - data = LittleEndianGuest::gtoh(data); - return error; - } - - template <class T> - Fault write(RequestPtr &req, T &data) - { -#if FULL_SYSTEM && THE_ISA == ALPHA_ISA - ExecContext *xc; - - // If this is a store conditional, act appropriately - if (req->isLocked()) { - xc = req->xc; - - if (req->isUncacheable()) { - // Don't update result register (see stq_c in isa_desc) - req->result = 2; - xc->setStCondFailures(0);//Needed? [RGD] - } else { - bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag); - Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag); - req->result = lock_flag; - if (!lock_flag || - ((lock_addr & ~0xf) != (req->paddr & ~0xf))) { - xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); - xc->setStCondFailures(xc->readStCondFailures() + 1); - if (((xc->readStCondFailures()) % 100000) == 0) { - std::cerr << "Warning: " - << xc->readStCondFailures() - << " consecutive store conditional failures " - << "on cpu " << req->xc->readCpuId() - << std::endl; - } - return NoFault; - } - else xc->setStCondFailures(0); - } - } - - // Need to clear any locked flags on other proccessors for - // this address. Only do this for succsful Store Conditionals - // and all other stores (WH64?). Unsuccessful Store - // Conditionals would have returned above, and wouldn't fall - // through. - for (int i = 0; i < system->execContexts.size(); i++){ - xc = system->execContexts[i]; - if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) == - (req->paddr & ~0xf)) { - xc->setMiscReg(TheISA::Lock_Flag_DepTag, false); - } - } - -#endif - return mem->prot_write(req->paddr, (T)htog(data), req->size); - } -*/ virtual bool misspeculating(); Fault instRead(RequestPtr &req) |